Nonvolatile memory

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EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage

EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage 150 150
Author(s): Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina

Abstract:

Designing compact and energy-efficient resistive RAM (RRAM) macros is challenging due to: 1) large read/write circuits that decrease storage density; 2) low-conductance cells that increase read latency; and 3) the pronounced effects of routing parasitics on high-conductance cell read energy. Multiple-bits-per-cell RRAM can boost storage density but has further challenges resulting from …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387566
Publisher: IEEE

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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150
Author(s): Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, Jae-Sun Seo

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 70 – 73
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3361011
Publisher: IEEE

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