Modeling

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Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 135 – 143
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704358
Publisher: IEEE

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APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications

APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications 150 150
Author(s): Bojun Zhang, Jinkai Wang, Zekun Wang, Xianan Zhu, Zhengkun Gu, Ziyuan Guo, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang

Abstract:

Computing-in-memory (CIM) has been widely investigated as a solution to the von Neumann bottleneck to reduce data transfer between memory and processor. However, existing CIM macros for neural network (NN) edge applications still suffer from high latency and energy consumption due to the correlation between data precision and the number …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720241
Publisher: IEEE

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FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing

FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing 150 150
Author(s): Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang

Abstract:

This article introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction (FE) and on-device few-shot learning (FSL). The accelerator addresses fundamental challenges of on-device learning (ODL) for resource-constrained edge applications through two synergistic modules: a parameter-efficient feature extractor (FE) employing weight clustering and an FSL classifier …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709217
Publisher: IEEE

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Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

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Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator 150 150
Author(s): Edward Jongyoon Choi, Byeongseon Choi, Jiho Chun, Minkyu Je, Bongjin Kim

Abstract:

Formal robustness verification of neural networks is essential for deploying machine learning (ML) systems in safety-critical applications. However, existing verification frameworks are predominantly software-based, incurring prohibitive computational costs and long runtimes, severely limiting scalability and practical deployment. Although symbolic interval analysis enables scalable over-approximate verification, its effectiveness is limited by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3707324
Publisher: IEEE

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A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery 150 150
Author(s): Xuchu Mu, Yang Jiang, Xin Ming, Bo Zhang, Rui P. Martins, Pui-In Mak

Abstract:

This article presents a reconfigurable switched-capacitor (SC) DC–DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702012
Publisher: IEEE

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A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS

A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS 150 150
Author(s): Hesham Beshary, Yikuan Chen, Ali M. Niknejad

Abstract:

This article presents a D-band 2-D scalable phased array that integrates a $2{\,}\times{\,} 2$ transceiving (TRX) radio frequency (RF) beamformer with on-chip antennas (OCAs) and a $\times 16$ local-oscillator (LO) multiplication chain. The 2-D array scalability is demonstrated by tiling $2{\,}\times{\,} 2$ chips into an array using a low-cost package to build a 16…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704818
Publisher: IEEE

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A Single-Lead ECG Wearable Sensor With 1.04 s Latency for Cardiac and Biometric Detection Tasks

A Single-Lead ECG Wearable Sensor With 1.04 s Latency for Cardiac and Biometric Detection Tasks 150 150
Author(s): Yuxin Ji, Chao Wang, Yuzhi Hao, Yang Zhao, Jian Zhao, Mingyi Chen, Guoxing Wang, Yong Lian, Yongfu Li

Abstract:

The wearable electrocardiogram (ECG) sensor has immense potential for cardiovascular healthcare monitoring. However, uploading ECG signals to server-side devices for diagnosis poses privacy risks. Multi-tasking ECG processors rely on multi-beat windows and complex models, leading to high latency and energy consumption that limit deployment in resource-constrained wearable devices. In this …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3700263
Publisher: IEEE

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PANDA: A Reconfigurable Seizure Prediction and Detection Neural Network Accelerator for Epilepsy Monitoring

PANDA: A Reconfigurable Seizure Prediction and Detection Neural Network Accelerator for Epilepsy Monitoring 150 150
Author(s): Siyuan Qiu, Xiaoyi Song, Xiangjie Song, Changchun Zhou, Xiaoyan Song, Jie Yang, Wenjin Wang, Yuchao Yang, Hailong Jiao

Abstract:

For effective healthcare management of epilepsy patients in a non-hospital environment, continuous monitoring of EEG signals is crucial, where wearable intelligent devices are essential. The existing seizure monitoring devices, however, cannot achieve high sensitivity, a short detection latency, a low false alarm rate (FAR), as well as ultra-low-power computing simultaneously. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699609
Publisher: IEEE

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