Low-pass filters

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A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification

A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification 150 150
Author(s): Patrice Abbie D. Legaspi, Shubham Yadav, Mark S. Oude Alink, Bram Nauta

Abstract:

Audio classification in edge devices has many applications and can be implemented at varying levels of complexity, typically consisting of a feature extractor followed by a classifier. Such devices are often always-on, constantly listening to their surroundings, and have a small form factor; therefore, they require low-power operation and high …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655426
Publisher: IEEE

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A 136.6-dB-DR 174.3-dB-FoMS Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop

A 136.6-dB-DR 174.3-dB-FoMS Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop 150 150
Author(s): Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Yeonjae Shin, Jeongyoon Wie, Seungyeob Baik, Hongki Kang, Minyoung Song, Jong-Hyeok Yoon, Junghyup Lee

Abstract:

This article presents a high-resolution, wide dynamic-range (DR) current-to-digital converter (IDC) capable of directly digitizing a broad range of bio-current signals. To achieve high resolution, the IDC uses a second-order continuous-time delta–sigma modulator (CT-DSM) architecture with a low-noise current-recycling operational amplifier (op-amp) and a highly linear pseudo-differential voltage-controlled oscillator (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653442
Publisher: IEEE

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A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET

A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET 150 150
Author(s): Huanan Guo, Yufeng Yao, Xiang Gao

Abstract:

To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design …

Published in: IEEE Solid-State Circuits Letters
Page(s): 5 – 8
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3637833
Publisher: IEEE

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