Logic gates

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A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load

A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load 150 150
Author(s): Seung Hun Choi, Jun Yeol An, Jaewoong Ahn, Si-Woo Kim, Jae-Youl Lee, Yoon-Kyung Choi, Hyung-Min Lee

Abstract:

On-cell touch flexible organic light-emitting diode (OLED) displays face significant display noise (D-noise) challenges due to large parasitic capacitance ( $C_{P}$ ). To address the limitations of conventional methods, this article proposes improved common-current subtraction (CCS), incorporating common-voltage subtraction (CVS) and common-charge subtraction (CQS) techniques. CVS enhances signal-to-noise ratio (SNR) by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3675678
Publisher: IEEE

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A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks

A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks 150 150
Author(s): Yi Xiang Huang, Y. S. Lin, P. S. Huang, E. Ray Hsieh

Abstract:

This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive …

Published in: IEEE Solid-State Circuits Letters
Page(s): 117 – 120
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3675063
Publisher: IEEE

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A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS 150 150
Author(s): Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yong Chen

Abstract:

This article reports a 40-GS/s 8-bit time-interleaved (TI) time-domain (TD) gated-ring-oscillator analog-to-digital converter (GRO-ADC). An interleaving number of 32 is achieved with a single-channel 8-bit GRO-ADC operating at 1.25 GS/s, leading to a low front-end design complexity compared to recently published arts. The sampling front end employs a linearity-enhanced boosted …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671459
Publisher: IEEE

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Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK

Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK 150 150
Author(s): Yingjie Li, Yifei Zhang, Haichuan Lin, Cheng Wang

Abstract:

Millions of quantum-bits (qubits) are envisioned for a fault-tolerant quantum computer. For scalability, silicon spin qubit stands out due to its compatibility with advanced CMOS processes. Silicon single-electron transistors (SETs) are widely adopted for the quantum state discrimination of spin qubits. For high-fidelity quantum logic gate and readout, the gate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671795
Publisher: IEEE

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Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure

Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure 150 150
Author(s): Kai Li, Keping Wang, Fanyi Meng, Kiat Seng Yeo, Kaixue Ma

Abstract:

This article presents a 13.7–41 GHz ultra-wideband frequency doubler with high efficiency and conversion gain (CG). The proposed cross-coupled push-push structure, in conjunction with the fourth-order transformer-based resonator and the series gate inductor, collaboratively shapes the input signal amplitude such that three distinct peaks emerge at different frequencies, thereby significantly improving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667289
Publisher: IEEE

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A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays

A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays 150 150
Author(s): Chih-Lung Lin, Cheng-Han Ke, Yu-Chang Chiu, Yuan-Yu Lai, Yi-Chien Chen, Cheng-Rui Lu, Yu-Hsiang Fu, Chih-Chuan Huang

Abstract:

This work presents a 5T2C pixel circuit for active-matrix (AM) micro-displays in near-eye display applications. The circuit supports monochrome micro light-emitting diode (micro-LED) displays with ultrahigh resolution of 7056 pixels per inch (PPI). The circuit is designed and fabricated based on medium-voltage (MV) devices from the 55-nm high-voltage (HV) CMOS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 89 – 92
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3667520
Publisher: IEEE

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A Pseudo-Series Resonance CMOS Oscillator

A Pseudo-Series Resonance CMOS Oscillator 150 150
Author(s): Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski

Abstract:

This article presents a single-core, low-phase-noise (PN) digitally controlled oscillator (DCO) employing a pseudo-series resonance (pseudo-SR) technique with a transformer-based resonator. The proposed pseudo-SR resonator offers two key advantages: 1) a low impedance with a 180° phase shift at the impedance pole, emulating series resonance (SR) to enable single-stage oscillation and reduce …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663515
Publisher: IEEE

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A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications

A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications 150 150
Author(s): Pei Qin, Junyu Wu, Taotao Xu, Yongchun Li, Wenjie Feng, Quan Xue, Wenquan Che

Abstract:

This article presents a reconfigurable dual-path dual-band low noise amplifier (LNA) for fifth generation (5G) millimeter-wave (mmW) communications. A novel band-switching input matching architecture based on the cross-connected transistors is proposed to achieve optimal dual-band input matching and $g_{m}$ -boosting. This architecture allows the dual-band input transistors to share …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3661593
Publisher: IEEE

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On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC

On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented …

Published in: IEEE Solid-State Circuits Letters
Page(s): 53 – 56
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656261
Publisher: IEEE

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