Logic gates

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EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage

EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage 150 150
Author(s): Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina

Abstract:

Designing compact and energy-efficient resistive RAM (RRAM) macros is challenging due to: 1) large read/write circuits that decrease storage density; 2) low-conductance cells that increase read latency; and 3) the pronounced effects of routing parasitics on high-conductance cell read energy. Multiple-bits-per-cell RRAM can boost storage density but has further challenges resulting from …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387566
Publisher: IEEE

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A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail

A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail 150 150
Author(s): Zhaoqing Wang, Mao Li, Suhwan Kim, Nachiket Desai, Ram K. Krishnamurthy, Xin Zhang, Mingoo Seok

Abstract:

This work presents a high-efficiency ten-level series-capacitor 24-to-1-V buck converter with three techniques to improve its efficiency and reliability. First, we propose a fast in situ efficiency tracking (FIT) technique to maximize efficiency across load conditions and process, voltage, and temperature (PVT) variations. The second technique is the power-FET …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3385662
Publisher: IEEE

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A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA

A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA 150 150
Author(s): Martin Lee, Motaz Mohamed Elbadry, Kambiz Moez

Abstract:

This article introduces a novel ultra-low-power reference-based low-noise amplifier (LNA) designed to reduce performance variations due to process, voltage, and temperature (PVT) when operating in the subthreshold region. The LNA is embedded within a reference circuit that directly controls the performance of the LNA over PVT variations. By combining the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3375154
Publisher: IEEE

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A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems

A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems 150 150
Author(s): Pierre-François Rüedi, Riccardo Quaglia, Hans-Rudolf Graf

Abstract:

We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc …

Published in: IEEE Solid-State Circuits Letters
Page(s): 106 – 109
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3370797
Publisher: IEEE

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A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing 150 150
Author(s): Niels Fakkel, Mohsen Mortazavi, Ramon W. J. Overwater, Fabio Sebastiano, Masoud Babaie

Abstract:

Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1433 – 1446
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3364968
Publisher: IEEE

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Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors

Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors 150 150
Author(s): Gautham Rangasamy, Zhongyunshen Zhu, Lars-Erik Wernersson

Abstract:

We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 8 – 12
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3355949
Publisher: IEEE

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HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism

HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism 150 150
Author(s): Qianqian Huang, Shaodi Xu, Ru Huang

Abstract:

Field-effect transistors (FETs) switched by quantum band-to-band tunneling (BTBT) mechanism, rather than conventional thermionic emission mechanism, are emerging as an exciting device candidate for future ultralow-power electronics due to their exceptional electronic properties of subthermionic subthreshold swing. However, fundamental limitations in drive current have hindered such technology encountering for high-performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 7
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2023.3338480
Publisher: IEEE

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