Integrated circuit interconnections

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A 3-D HBI Compliant 1.536 TB/s/mm2 Bandwidth Scalable Attention Accelerator With 22.5-GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3

A 3-D HBI Compliant 1.536 TB/s/mm2 Bandwidth Scalable Attention Accelerator With 22.5-GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3 150 150
Author(s): Prerna Budhkar, Mirco Sciulli, Srivatsa Rangachar Srinivasa, Gauthaman Murali, Ragh Kuttappa, Paolo Aseron, Trang Nguyen, Vinayak Honkote, Tanay Karnik

Abstract:

This letter presents a novel hardware accelerator compatible with <3- $\mu $ m pitch 3-D Cu-Cu hybrid bonding interconnect (HBI) technology, particularly designed to efficiently execute multihead attention (MHA) of encoder transformer models. We present an accelerator that addresses performance losses due to low precision models by incorporating specialized hardware optimizations …

Published in: IEEE Solid-State Circuits Letters
Page(s): 69 – 72
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3659575
Publisher: IEEE

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Modern Wireline Transceivers

Modern Wireline Transceivers 150 150
Author(s): Tony Chan Carusone, Timothy O. Dickson, Samuel Palermo, Sudip Shekhar, Mozhgan Mansuri

Abstract:

Over the past two decades, ever-increasing network bandwidth (BW) demands in data centers and high-performance computing systems have fueled exponential growth in per-lane serial link data rates. To keep up with this demand and enable faster communication over BW-limited electrical channels, wireline transceiver architectures and circuit topologies have rapidly evolved …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 395 – 422
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3642231
Publisher: IEEE

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kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing

kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing 150 150
Author(s): Anjali Agrawal, Zhenghong Chen, Braden E. Desman, Jinhua Wang, Akiyoshi Tanaka, Fahim Foysal, Charles D. Hess, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun

Abstract:

This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks. To preserve garment comfort and flexibility, kNOT eliminates bulky boards and interposers through direct-die attachment to embroidered yarns. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 103 – 115
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624099
Publisher: IEEE

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SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory 150 150
Author(s): Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu

Abstract:

This article presents SHINSAI—a 586 mm2 reusable active through-silicon via (TSV) interposer addressing key challenges in multi-chiplet integration (MCI) architectures. While active interposers overcome fundamental limitations of passive counterparts by integrating functional circuitry, existing solutions face three critical constraints: 1) non-recurring engineering (NRE) costs from application-specific interposers negating chiplet reuse benefits; 2) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 90 – 102
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623630
Publisher: IEEE

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Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling

Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling 150 150
Author(s): Anup Ashok Kedilaya, Sirish Oruganti, Nishant Gupta, Xiuhao Zhang, Ilya Karpov, Mark A. Anders, Jaydeep P. Kulkarni

Abstract:

Advances in process technology enabling backside metals (BSMs) and contacts offer new design–technology co-optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3-nm nodes. This work exploits backside (BS) contact technology within standard cells to extend both signal and clock routing to BSM layers, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 107 – 115
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617784
Publisher: IEEE

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3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency

3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency 150 150
Author(s): Janak Sharda, Madison Manley, Jungyoun Kwak, Chinsung Park, Muhannad Bakir, Shimeng Yu

Abstract:

Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures, such as 2.5-D integration of memory with logic, have been proposed; however, the bandwidth limits the throughput of the complete system. Recent works have proposed memory on logic systems, where high bandwidth memory (HBM) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 116 – 122
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617298
Publisher: IEEE

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