Gain

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A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration

A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a low-spur, low-jitter fractional-N digital phase-locked loop (DPLL) employing an analog pre-distortion digital-to-time converter (APD-DTC) to suppress fractional spurs by compensating for both second- and third-order nonlinearities without using complex digital pre-distortion. To support background calibration, a spur-level detection scheme using phase detector gain (PDG) is proposed …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706350
Publisher: IEEE

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A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop

A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop 150 150
Author(s): Junyuan Su, Yuxuan Hu, Zherui Zhang, Lei Wang, Yuncai Zhuang, Fei Song, Jiayoon Ru

Abstract:

This article introduces a CP-sampling (CS)-fusion PLL architecture that combines the advantages of PFD-CP PLLs (robust and speedy locking) and sampling PLLs (low jitter/power) in a single loop. The PFD sends pulsewidth-modulation (PWM) pulses to a merged $mathbf {G_{m}}$ /CP (GCP) block so that the phase error …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 20
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704989
Publisher: IEEE

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A Capacitor-Free Hybrid-Process Low Dropout Regulator With Ultrahigh-Gain Amplifier and Super Source Follower for 0.297 mV/A Load Regulation and 0.024 mV/V Line Regulation

A Capacitor-Free Hybrid-Process Low Dropout Regulator With Ultrahigh-Gain Amplifier and Super Source Follower for 0.297 mV/A Load Regulation and 0.024 mV/V Line Regulation 150 150
Author(s): Yu-Ting Huang, Xiao-Quan Wu, Chi-Yu Chen, Po-Jui Chiu, Chien-Wei Cho, Tz-Wun Wang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Sheng-Hsi Hung, Chih-Fang Huang, Philex Ming-Yan Fan, Tsorng-Juu Liang, Hann-Huei Tsai

Abstract:

The proposed capacitor-free hybrid-process low-dropout regulator (LDO) achieves 900-mA maximum current capacity and 99.99% peak current efficiency with 90 $\mu $ A quiescent current. By combining GaN and silicon processes, the proposed Ultrahigh gain amplifier (UHGA) enables a high loop gain to achieve 0.297-mV/A load regulation and 0.024-mV/V line regulation. Furthermore, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702962
Publisher: IEEE

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A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS

A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS 150 150
Author(s): Hesham Beshary, Yikuan Chen, Ali M. Niknejad

Abstract:

This article presents a D-band 2-D scalable phased array that integrates a $2{\,}\times{\,} 2$ transceiving (TRX) radio frequency (RF) beamformer with on-chip antennas (OCAs) and a $\times 16$ local-oscillator (LO) multiplication chain. The 2-D array scalability is demonstrated by tiling $2{\,}\times{\,} 2$ chips into an array using a low-cost package to build a 16…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704818
Publisher: IEEE

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A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy

A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy 150 150
Author(s): Seonghyun Park, Song-I Cheon, Haidam Choi, Sein Oh, Sohmyung Ha, Minkyu Je

Abstract:

This article presents an electrical bio-impedance (bioZ) spectroscopy integrated circuit (IC) that achieves both high-throughput and high-accuracy. The proposed phase-locked sampling (PLS) scheme, which employs a sampling phase-locked loop (SPLL) and a reference resistor ( $R_{\textit {REF}}$ ), enables fast and precise impedance demodulation. By extracting the impedance components through sampling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704052
Publisher: IEEE

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A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS

A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS 150 150
Author(s): Sungwon Kwon, Byung-Wook Min

Abstract:

This article presents a W-band active bidirectional vector-sum phase shifter (Bi-VSPS) using a bidirectional phase-inverting variable-gain amplifier (Bi-PIVGA) with back-gate biasing in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS. The Bi-PIVGA employs a neutralization technique that cancels the gate-to-drain capacitances of both active and inactive transistors in each signal direction. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699765
Publisher: IEEE

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An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique 150 150
Author(s): Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang

Abstract:

This article presents an incremental noise-shaping (NS) pipeline analog-to-digital converter (ADC) featuring a single-amplification-based kT/C noise cancellation technique. By pre-amplifying the frontend sampling kT/C noise onto the capacitive digital-to-analog converter (CDAC) of the backend NS successive approximation register (SAR) quantizer, the proposed architecture eliminates the repeated amplifications typically …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698875
Publisher: IEEE

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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