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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4 GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4558 – 4571
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS

A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS 150 150
Author(s): Zhicheng Lin, Hiu Lok Tam, Hao Guo, Xiaoyue Xia, Zijun Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 252–283-GHz amplifier-last transmitter (TX) and amplifier-first receiver (RX) wireless front end in standard 65-nm bulk CMOS technology, targeting IEEE 802.15.3d/802.15.3-compliant high-speed point-to-point wireless communications. To overcome the challenges of limited transistor gain and high passive loss that often limit the implementation of J-band RF amplifiers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730962
Publisher: IEEE

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A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification 150 150
Author(s): Hongjiang Chen, Jingxiang Wang, Kaize Zhang, Shizhan Mo, Liang Qi, Chao Zhao, Hao Zhang, Zhang Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730470
Publisher: IEEE

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A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications

A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications 150 150
Author(s): Mohamed Eleraky, Alessandro Novello, Giorgio Cristiano, Basem Abdelaziz Abdelmagid, Yuqi Liu, Jianping Zeng, Jinglong Xu, Boce Lin, Jonas Nann, Hangxing Liu, Marco Saif, Niccolò Villaggi, Lavinia Recchioni, Tzu-Yuan Huang, Thomas Burger, Thomas Kleier, Hua Wang

Abstract:

This article presents an eight-channel dual-polarized Ku-band transmitter (Tx) beamformer integrated circuit (BFIC) fabricated in a 22-nm GlobalFoundries FDSOI process. Each channel integrates independent phase and gain control utilizing a 7-bit active phase shifter (PS) and a 5.5-bit attenuator (ATT). To mitigate performance degradation caused by load impedance variations in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3727539
Publisher: IEEE

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Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing

Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing 150 150
Author(s): Sherif Ghozzy, Muhamed Allam, Emir Ali Karahan, Zheng Liu, Kaushik Sengupta

Abstract:

A critical challenge in scaling up high-frequency wireless communication in the millimeter-Wave (mmWave) spectrum has been poor energy efficiency of the constituent transceivers, particularly on the highly energy constrained user equipment (UE). Receiving spectrally-efficient wireless signals (e.g., 64-quadrature amplitude modulation (QAM) etc.) require coherent transceivers with programmable frequency synthesizers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720585
Publisher: IEEE

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A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation

A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation 150 150
Author(s): Yongqi Hu, Jue Huang, Chenkang Ning, Yumeng Yuan, Hao Xu, Na Yan, Xufeng Kou

Abstract:

This article presents a calibration-free fractional-N cascaded phase-locked loop (PLL) employing a sampling phase detector (SPD)-bypass-based phase-domain oversampling noise-and-spur cancellation (P-OSNSC) technique. By incorporating an oversampling cancellation path that eliminates the gain errors and noise cancellation bandwidth limitation introduced by the SPD, the proposed architecture suppresses noise from the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3725003
Publisher: IEEE

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A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS

A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS 150 150
Author(s): Hsiang-Chun Cheng, Mayank Palaria, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen

Abstract:

This letter presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 222 – 225
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717659
Publisher: IEEE

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A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

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A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter

A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter 150 150
Author(s): Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon

Abstract:

This article presents a 31.5–36 GHz digitally assisted gain-boosting (GB) charge-sharing locking (CSL) phase-locked loop (PLL) that achieves record-low reference spurs while maintaining sub-60 fs integrated jitter. In conventional CSL PLLs, reference spur suppression is fundamentally traded against loop bandwidth, whereas ping-pong CSL (PP-CSL) approaches typically require complex duty-cycle calibration. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721352
Publisher: IEEE

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