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A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References

A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References 150 150
Author(s): Raghav Bansal, Shouri Chatterjee

Abstract:

This article presents a fully integrated output-capacitor-less (OCL) multi-feedback-loop low-dropout regulator (LDO) with an in-built single bipolar junction transistor (BJT)-based voltage and current reference (VCR) for energy-harvesting Internet of Things (IoT) devices. The proposed architecture comprises four loops, which significantly enhance the DC regulation and transient performance of the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3694415
Publisher: IEEE

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A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity

A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity 150 150
Author(s): Feng Cheng, Jianlin Xia, Encheng Zhu, Long Zhang, Zhongyuan Fang, Xiaofeng Sun, Dejin Wang, Shaoping Li, Jing Zhu, Yongjia Li, Weifeng Sun

Abstract:

This article proposes a hybrid magnetic current sensor achieving a 15-MHz bandwidth within a compact 2.7-mm2 area. To mitigate the pole–zero mismatch inherent in the two-stage integrator topology, a dual-output Gm-C integrator with subtractor-based compensation is proposed, achieving a ±0.8% local gain non-uniformity. A wideband feedforward ripple suppression scheme cancels …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692476
Publisher: IEEE

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A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

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A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier

A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier 150 150
Author(s): Yihang Cheng, Yihan Zhang, Huaqiang Wu, Sining Pan

Abstract:

This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by $4\times $ compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier …

Published in: IEEE Solid-State Circuits Letters
Page(s): 93 – 96
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3668876
Publisher: IEEE

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A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM

A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM 150 150
Author(s): Yiming Han, Linran Zhao, Yaoyao Jia

Abstract:

This article presents a noise-shaping successive approximation register (NS-SAR)-based direct-digitizing electrophysiological (ExG) sensing frontend (SFE) fabricated in a standard 180-nm CMOS process. To address the challenges of large motion artifacts and high electrode–tissue impedance (ETI), we propose three key innovations in our proposed SFE that enable accurate ExG …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3674986
Publisher: IEEE

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Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation

Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation 150 150
Author(s): Hao Yu, Zhaojing Fu, Lianbo Liu, Qiang Zhou, Taiyun Chi, Sensen Li

Abstract:

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667125
Publisher: IEEE

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A High-Power Wideband Sub-THz Power Amplifier With Asymmetric Slotline-Based Series–Parallel Combiner in 130-nm SiGe BiCMOS Technology

A High-Power Wideband Sub-THz Power Amplifier With Asymmetric Slotline-Based Series–Parallel Combiner in 130-nm SiGe BiCMOS Technology 150 150
Author(s): Gunwoo Park, Hyunjoon Kim, Sanggeun Jeon

Abstract:

This article presents a high-power, wideband sub-terahertz power amplifier (PA) implemented in a 130-nm SiGe BiCMOS technology. The PA features a novel asymmetric slotline-based series–parallel combiner (ASSPC) for output power combining. The ASSPC provides both low-loss, wideband combining and efficient admittance matching for four differential cascode PA unit cells, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656477
Publisher: IEEE

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This letter presents a low-jitter digital harmonic-mixing fractional- $N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that …

Published in: IEEE Solid-State Circuits Letters
Page(s): 57 – 60
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS

A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS 150 150
Author(s): Xiongshi Luo, Xuewei You, Zhenghao Li, Hongzhi Wu, Yangyi Zhang, Fuzhan Chen, Xuxu Cheng, Wentao Zhou, Quan Pan

Abstract:

A dc-coupled analog single-ended (SE) transceiver (TRX) front-end supporting 224 Gb/s/lane is presented. It features SE-to-differential (S2D) and differential-to-SE (D2S) conversion, power-efficient broadband analog equalization, and noise suppression. Both the transmitter and receiver front-ends adopt pseudodifferential structures with dual-loop regulators to achieve a high power supply rejection …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3644437
Publisher: IEEE

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