Gain

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A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping

A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping 150 150
Author(s): Jihang Gao, Yaohui Luan, Siyuan Ye, Jiajia Cui, Xinhang Xu, Linxiao Shen

Abstract:

This article presents a calibration-free pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the proposed cross-stage gain-mismatch-error shaping (CS-GMES) mechanism. The CS-GMES is realized by including the entire 2nd stage into MES operation to unify the gain error and the 2nd-stage mismatch error. A feedback capacitor provides cross-stage connection and mismatch …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624412
Publisher: IEEE

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A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology

A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology 150 150
Author(s): Ethan Chou, Hesham Beshary, Nima Baniasadi, Ali M. Niknejad

Abstract:

This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 349 – 352
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626442
Publisher: IEEE

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Frequency-Agile Self-Interference Cancellation in a Wideband Compact Full-Duplex Receiver Using Cascaded Low-Noise and High-Delay-Bandwidth-Product APFs

Frequency-Agile Self-Interference Cancellation in a Wideband Compact Full-Duplex Receiver Using Cascaded Low-Noise and High-Delay-Bandwidth-Product APFs 150 150
Author(s): Xingyu Ma, Wei Li, Shijiao Dong, Ruiyu Lyu, Fan Chen, Yunyou Pu, Chuangguo Wang, Hongtao Xu

Abstract:

Wideband self-interference cancellation (SIC) in a full-duplex (FD) system requires the cancellers to achieve flat nanosecond-scale RF delay while minimizing the noise penalty to the receiver (RX). This work proposes: 1) cascadable hybrid low-noise first-order all-pass filters (APFs) in the first tap of the RF canceller to reduce the noise figure (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618610
Publisher: IEEE

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A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification 150 150
Author(s): Jeroen Ponte, Roel Plompen, Emiel Zijlma, Eric A. M. Klumperink, Harijot Singh Bindra, Bram Nauta

Abstract:

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611114
Publisher: IEEE

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue

Abstract:

This work presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver (ORX) with a linear analog front-end (AFE) and an integrated sampler. The AFE employs a transadmittance-stage transimpedance-stage (TAS-TIS) topology, replacing conventional CML-based variable gain amplifiers (VGAs) and post-amplifiers, avoiding continuous-time linear equalizers and passive inductors while preserving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607107
Publisher: IEEE

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A 4 × 50 Gb/s 2.9-pJ/b NRZ VCSEL-Based Co-Packaged Optical Link With Fiber Termination

A 4 × 50 Gb/s 2.9-pJ/b NRZ VCSEL-Based Co-Packaged Optical Link With Fiber Termination 150 150
Author(s): Sashank Krishnamurthy, Susnata Mondal, Junyi Qiu, Joseph Kennedy, Soumya Bose, Tolga Acikalin, Shuhei Yamada, James Jaussi, Mozhgan Mansuri

Abstract:

A four-channel vertical cavity surface-emitting laser (VCSEL)-based co-packaged optical (CPO) transceiver (TRX) is demonstrated, integrating a photodiode (PD) array, a trans-impedance amplifier front-end integrated circuit (TIA-FE IC), an electrical receiver (RX) IC, and optical fiber termination on a single package on the receive side. The transmitter (TX) counterpart incorporates …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3600662
Publisher: IEEE

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A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, C. Patrick Yue

Abstract:

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 273 – 276
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3603569
Publisher: IEEE

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A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver

A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver 150 150
Author(s): Yihao Yang, Dan Li, Nan Qi, Binhao Wang

Abstract:

This letter describes an ultra-low-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3584266
Publisher: IEEE

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