Gain

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An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors

An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors 150 150
Author(s): Xinyi Wu, Chenxu Zhao, Hui Chen, Xun Bao, Yaolong Hu, Aoyang Zhang, Leibo Liu

Abstract:

This letter presents a compact, multiband reflection-type phase shifter (RTPS) implemented in 65-nm CMOS that overcomes the narrowband limitations of conventional passive loads. The proposed design utilizes an inductive-load modulation. By injecting a secondary signal to actively manipulate the magnetic flux, the equivalent inductance is boosted to enable operation across …

Published in: IEEE Solid-State Circuits Letters
Page(s): 170 – 173
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3694867
Publisher: IEEE

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A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only …

Published in: IEEE Solid-State Circuits Letters
Page(s): 178 – 181
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

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A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The …

Published in: IEEE Solid-State Circuits Letters
Page(s): 186 – 189
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

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A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS

A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS 150 150
Author(s): Sungwon Kwon, Byung-Wook Min

Abstract:

This article presents a W-band active bidirectional vector-sum phase shifter (Bi-VSPS) using a bidirectional phase-inverting variable-gain amplifier (Bi-PIVGA) with back-gate biasing in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS. The Bi-PIVGA employs a neutralization technique that cancels the gate-to-drain capacitances of both active and inactive transistors in each signal direction. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699765
Publisher: IEEE

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An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique 150 150
Author(s): Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang

Abstract:

This article presents an incremental noise-shaping (NS) pipeline analog-to-digital converter (ADC) featuring a single-amplification-based kT/C noise cancellation technique. By pre-amplifying the frontend sampling kT/C noise onto the capacitive digital-to-analog converter (CDAC) of the backend NS successive approximation register (SAR) quantizer, the proposed architecture eliminates the repeated amplifications typically …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698875
Publisher: IEEE

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References

A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References 150 150
Author(s): Raghav Bansal, Shouri Chatterjee

Abstract:

This article presents a fully integrated output-capacitor-less (OCL) multi-feedback-loop low-dropout regulator (LDO) with an in-built single bipolar junction transistor (BJT)-based voltage and current reference (VCR) for energy-harvesting Internet of Things (IoT) devices. The proposed architecture comprises four loops, which significantly enhance the DC regulation and transient performance of the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3694415
Publisher: IEEE

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A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity

A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity 150 150
Author(s): Feng Cheng, Jianlin Xia, Encheng Zhu, Long Zhang, Zhongyuan Fang, Xiaofeng Sun, Dejin Wang, Shaoping Li, Jing Zhu, Yongjia Li, Weifeng Sun

Abstract:

This article proposes a hybrid magnetic current sensor achieving a 15-MHz bandwidth within a compact 2.7-mm2 area. To mitigate the pole–zero mismatch inherent in the two-stage integrator topology, a dual-output Gm-C integrator with subtractor-based compensation is proposed, achieving a ±0.8% local gain non-uniformity. A wideband feedforward ripple suppression scheme cancels …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692476
Publisher: IEEE

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