Gain

  • No Comments

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 150 150
Author(s): Yunfan Gao, Minghan Liu, Mengting Yan, Cristian Cassella, Miriam Leeser, Marvin Onabajo

Abstract:

This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct downconversion mixing, which avoids a dedicated LO generator, coupler, or …

Published in: IEEE Solid-State Circuits Letters
Page(s): 258 – 261
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725828
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 250 – 253
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs

A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs 150 150
Author(s): Abhishek Kumar, Nagendra Krishnapura

Abstract:

Sub-sampling PLLs use a transconductor following the sampling phase detector. To reduce the loop-filter capacitor size, a small transconductance with polarity switching can drive a switched-capacitor loop filter; however, slow settling introduces uncertainty in the PLL parameters, and excess output noise directly contributes to PLL jitter. Realizing a small transconductance …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3743715
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems

A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems 150 150
Author(s): Fangming Lou, Haoqiang Deng, Tuo Li, Kai Yuan, Ka Nang Leung, Junmin Jiang, Guoqing Li, Xun Liu

Abstract:

This article proposes a low-dropout regulator (LDO) using a flipped voltage follower (FVF) topology for wide-load-range and low-noise applications. The proposed LDO features a fast load transient response and wide-spectrum power-supply rejection (PSR) performance. To optimize frequency responses at light load and improve PSR performance in the mid-frequency band, an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3739837
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation

A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation 150 150
Author(s): Xuansheng Ji, Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Abstract:

This article presents a coherent polar phase-tracking receiver (PT-RX) for low-power Internet-of-Things(IoT) applications that supports Gaussian frequency-shift keying (GFSK), quadrature amplitude modulation (QAM), and amplitude phase shift keying (APSK). Existing single-path closed-loop receivers achieve low power but suffer from a fundamental tradeoff between loop stability and adjacent channel rejection (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5370 – 5382
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712802
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation

An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation 150 150
Author(s): Yanchao Liu, Kaihang Wang, Yang Li, Xiaohua Yu, Ronghua Ni

Abstract:

This article presents a high-performance 13.2-GHz fractional-N sampling phase-locked loop (PLL). To overcome the nonlinearity bottlenecks inherent in edge-restoring buffers used in conventional digital-to-time converters (DTCs), an intrinsically linear variable-slope sampling phase detector (VS-SPD) is proposed. By seamlessly merging an RC delay network with a sampling phase detector (SPD), the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735859
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier

A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier 150 150
Author(s): Guo Wei, Rui Zhang, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This article presents a 14-bit 1-GS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) in a 28 nm CMOS process, targeting the optimization of conversion speed and latency. The implemented ADC adopts a two-stage architecture that integrates a residue amplifier (RA) assisted 4-bit/cycle sub-quantizer to tackle the accuracy bottleneck of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738437
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression

A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression 150 150
Author(s): Yuzhou Xiong, Guolong Fu, Xianghui Zhang, Shian Wang, Yuke Shen, Yuhua Liang, Zhong Tang, Yanbo Zhang, Zhangming Zhu

Abstract:

This article presents a multi-rate successive approximation register (SAR)-assisted exponential-incremental (EI) pipeline analog-to-digital converter (ADC) for wireless communication applications. By employing a multi-rate scheme, the ADC harnesses the benefits of oversampling and noise-shaping (NS) techniques while avoiding bandwidth (BW) degradation. To further increase the BW to hundreds of megahertz …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733687
Publisher: IEEE

View on IEEE Xplore

Search this website