Energy efficiency

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A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality

A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality 150 150
Author(s): Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang

Abstract:

Augmented reality (AR) has been applied to various mobile applications. Modern AR algorithms include neural networks, such as convolutional neural networks (CNNs) and graph convolutional networks (GCNs). The high computational complexity of these networks poses challenges for real-time operation on energy-constrained devices. This article presents the first energy-efficient hybrid CNN-GCN …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3391665
Publisher: IEEE

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A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching

A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching 150 150
Author(s): Xiaoyu Feng, Wenyu Sun, Chen Tang, Xinyuan Lin, Jinshan Yue, Huazhong Yang, Yongpan Liu

Abstract:

Voxel-based point cloud networks composed of multiple kinds of sparse convolutions (SCONVs) play an essential role in emerging applications such as autonomous driving and visual navigation. Many researchers have proposed sparse processors for image applications. However, they cannot properly deal with three problems in the point cloud, including low efficiency …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3386878
Publisher: IEEE

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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures 150 150
Author(s): Saion K. Roy, Naresh R. Shanbhag

Abstract:

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 22 – 30
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3381888
Publisher: IEEE

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PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs

PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs 150 150
Author(s): Amitesh Sridharan, Jyotishman Saikia, Anupreetham, Fan Zhang, Jae-Sun Seo, Deliang Fan

Abstract:

We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 102 – 105
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3369058
Publisher: IEEE

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A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators 150 150
Author(s): Martijn Timmermans, Kyle van Oosterhout, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore

Abstract:

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1194 – 1203
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3352735
Publisher: IEEE

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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150
Author(s): Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, Jae-Sun Seo

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 70 – 73
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3361011
Publisher: IEEE

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