Delays

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Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines

Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines 150 150
Author(s): Sasank Garikapati, Aravind Nagulu, Igor Kadota, Mostafa Essawy, Tingjun Chen, Shibo Wang, Tanvi Pande, Arun S. Natarajan, Gil Zussman, Harish Krishnaswamy

Abstract:

The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3351615
Publisher: IEEE

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A 6 to 12-GHz Fractional- $N$ Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

A 6 to 12-GHz Fractional- $N$ Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays 150 150
Author(s): Aditya Narayanan, Abhishek Bhat, Nagendra Krishnapura

Abstract:

This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3373620
Publisher: IEEE

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking 150 150
Author(s): Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1225 – 1234
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3355447
Publisher: IEEE

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