Delays

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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 250 – 253
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

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A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C

A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C 150 150
Author(s): Wenbo Zhang, Fantao Wang, Junyi Liu, Yanzhao Ma

Abstract:

This letter presents a delay-compensated RC relaxation oscillator for enhanced frequency stability. The proposed architecture employs a peak-sampling circuit to detect the charging-capacitor peak voltage. A feedback loop composed of an error amplifier and compensation resistors adaptively raises the capacitor DC baseline to compensate for comparator-delay-induced frequency error, while phase-alternating …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3738818
Publisher: IEEE

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Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links

Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links 150 150
Author(s): Susnata Mondal, Sashank Krishnamurthy, Shuhei Yamada, Zhaokai Liu, Junyi Qiu, Soumya Bose, Zuoguo Wu, Gerald Pasdast, James Jaussi, Mozhgan Mansuri

Abstract:

This article presents a Universal Chiplet Interconnect Express (UCIe)-compliant die-to-die (D2D) transceiver PHY for chiplet interconnects over a standard organic package, along with an extension to off-package interconnects over printed circuit board (PCB) channels. The transceiver introduces several power-efficient, high-performance techniques, including an impedance-invariant passive continuous-time linear equalizer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737168
Publisher: IEEE

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A Clock-Edge Architecture for Processor Clock-Power Reduction

A Clock-Edge Architecture for Processor Clock-Power Reduction 150 150
Author(s): Yimai Peng, Daniel J. Yingling, Basma Hajri, Robert J. Vachon, Fikre Gebreyohannes, Vincent Li, Ghanshyam Chhetri, Keith A. Bowman

Abstract:

A clock-edge architecture (CEA), consisting of an adaptive clock duty-cycle controller (DCC), dual-edge-triggered (DET) flip-flops (FFs), and DET clock-gating circuits (CGCs), enables a processor to achieve the same performance as a conventional (CNV) design while operating at half the clock frequency (F ${}_{\mathrm {CLK}}$ ), thereby significantly reducing the clock power. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730222
Publisher: IEEE

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Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 159 – 166
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

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3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems

3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems 150 150
Author(s): Arya Upadhyay

Abstract:

Moving sensor data and neural-network operands through conventional external-memory hierarchies can constitute a substantial fraction of the energy required for edge inference. Motivated by a three-tier near-sensor organization, this work evaluates memory localization using a controlled architecture-level study and an independent transistor-level communication-link analysis. Five convolution configurations are evaluated on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3735890
Publisher: IEEE

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An Eight-Channel Direct Analog Sensor Fusion Core for On-the-Spot Time-Series Analysis in Edge AI

An Eight-Channel Direct Analog Sensor Fusion Core for On-the-Spot Time-Series Analysis in Edge AI 150 150
Author(s): Jia-le Cui, Yasuko Matsubara, Yasushi Sakurai, Noriyuki Miura

Abstract:

A time-series analysis on multi-channel sensor signals is critical for wide-range Artificial Intelligence (AI) applications, such as in a field of mobility, robot, and infrastructure monitoring. Edge-device data collection followed by cloud-based analysis suffers from high latency and power consumption. This article presents an edge-AI-oriented sensor fusion architecture, performing analog …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726487
Publisher: IEEE

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A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications

A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications 150 150
Author(s): Xichen Li, Ahmed Refaat Aboulsaad, Elpida Karapepera, Yi-Hsiang Huang, Po-Hao Cheng, Charles Chien, Jacques Christophe Rudell

Abstract:

Future full-duplex (FD) radio systems require highly tunable self-interference (SI) cancellers with rapid adaptation to mitigate dynamic SI profiles in wireless environments. This article presents a 2.4-GHz RF SI canceller chip with extensive tuning capabilities that operates with a machine-learning (ML)-augmented adaptation loop for FD transceivers. The proposed design …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715631
Publisher: IEEE

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A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS 150 150
Author(s): Sangwan Lee, Heedo Jeong, Hanhee Jo, Hwanseok Jung, Jaeduk Han

Abstract:

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713392
Publisher: IEEE

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