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A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency

A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency 150 150
Author(s): Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Seok-Jun Lee, Sung-Wan Hong

Abstract:

This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting …

Published in: IEEE Solid-State Circuits Letters
Page(s): 233 – 236
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3594739
Publisher: IEEE

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A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization

A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization 150 150
Author(s): Cai Li, Kaize Zhou, Junyi Qian, Haochang Zhi, Weiwei Shan

Abstract:

This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing …

Published in: IEEE Solid-State Circuits Letters
Page(s): 229 – 232
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3593960
Publisher: IEEE

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A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS

A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS 150 150
Author(s): Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua

Abstract:

This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an …

Published in: IEEE Solid-State Circuits Letters
Page(s): 217 – 220
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3591570
Publisher: IEEE

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A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150
Author(s): Junhui Gu, John Ma, Azhar Ahmed Chowdhury, Jianmin Guo, Xin Zhang, Jackson Ding, Hui Wang, Ken Chang

Abstract:

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1289 – 1298
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545483
Publisher: IEEE

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