Delays

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Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles

Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles 150 150
Author(s): Junyi Qian, Lishuo Deng, Cai Li, Yizhi Ding, Weiwei Shan

Abstract:

Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this …

Published in: IEEE Solid-State Circuits Letters
Page(s): 25 – 28
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3645701
Publisher: IEEE

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A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a $27\mu $ m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 373 – 376
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3636192
Publisher: IEEE

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A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors

A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors 150 150
Author(s): Xiuzhi Zhao, Liheng Liu, Shi Chen, Tianxiang Qu, Qinjing Pan, Dan Li, Gan Guo, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents an ultralow-noise, power-efficient, and pulse-width modulation (PWM)-dimming-tolerant photocurrent readout circuit for under-display ambient light sensor (ALS). A transimpedance amplifier (TIA) with a feedback diode achieves G $\Omega $ -level resistance and 6 fA/ $\surd $ Hz input current noise, enabling sub-pA resolution. Instability and noise folding are mitigated at …

Published in: IEEE Solid-State Circuits Letters
Page(s): 361 – 364
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626378
Publisher: IEEE

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Frequency-Agile Self-Interference Cancellation in a Wideband Compact Full-Duplex Receiver Using Cascaded Low-Noise and High-Delay-Bandwidth-Product APFs

Frequency-Agile Self-Interference Cancellation in a Wideband Compact Full-Duplex Receiver Using Cascaded Low-Noise and High-Delay-Bandwidth-Product APFs 150 150
Author(s): Xingyu Ma, Wei Li, Shijiao Dong, Ruiyu Lyu, Fan Chen, Yunyou Pu, Chuangguo Wang, Hongtao Xu

Abstract:

Wideband self-interference cancellation (SIC) in a full-duplex (FD) system requires the cancellers to achieve flat nanosecond-scale RF delay while minimizing the noise penalty to the receiver (RX). This work proposes: 1) cascadable hybrid low-noise first-order all-pass filters (APFs) in the first tap of the RF canceller to reduce the noise figure (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618610
Publisher: IEEE

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A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

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A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology

A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology 150 150
Author(s): Bram Veraverbeke, Filip Tavernier

Abstract:

All cryo-CMOS quantum-classical control interfaces require an analog-to-digital converter (ADC) bridging the analog qubits and the digital control logic. Dynamic comparators play a crucial role in the precision, speed, and power consumption of these ADCs. Yet, their performance is severely impacted by the cryogenic environment. Therefore, this letter benchmarks, for …

Published in: IEEE Solid-State Circuits Letters
Page(s): 317 – 320
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3618161
Publisher: IEEE

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An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation

An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation 150 150
Author(s): Yongjia Li, Jianlin Xia, Feng Cheng, Yifan Cao, Jin Wu, Encheng Zhu, Xiaofeng Sun, Dejin Wang, Long Zhang, Zhongyuan Fang, Weifeng Sun

Abstract:

This letter presents an RC oscillator featuring a mixed-signal compensation loop that simultaneously mitigates comparator offset, loop delay, switch on-resistance, and temperature dependency. The oscillator employs an auxiliary comparator, a charge pump, and a differential difference amplifier (DDA)-based main comparator to suppress ramping voltage overshoots caused by device and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 333 – 336
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3615833
Publisher: IEEE

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A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration

A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration 150 150
Author(s): Munjae Chae, Seheon Jang, Seungjae Lee, Jaehyouk Choi

Abstract:

This work presents a 10.0–11.5-GHz fractional- $N$ digital phase-locked loop (DPLL) using the quantization-error-compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay ( $T_{\mathrm {S}}$ ) and the dynamic delay ( $T_{\mathrm {D}}$ ) required for removing the delta-sigma modulator’s ( $\Delta \Sigma $ M) quantization-error (Q-error). Since the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611417
Publisher: IEEE

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A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants

A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 150 150
Author(s): Ronald Wijermars, Yi-Han Ou-Yang, Sijun Du, Dante G. Muratore

Abstract:

This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm …

Published in: IEEE Solid-State Circuits Letters
Page(s): 305 – 308
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3611484
Publisher: IEEE

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