Delays

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay

A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay 150 150
Author(s): Giovanni Scarlato, John R. Long

Abstract:

A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with $12~\pm ~2$ -ps group delay and >10-dB return loss across 90 GHz. Bandwidth …

Published in: IEEE Solid-State Circuits Letters
Page(s): 65 – 68
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3661366
Publisher: IEEE

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A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm 150 150
Author(s): Brian Zimmer, Stephen G. Tell, C. Thomas Gray

Abstract:

This work presents a self-timed die-to-die link that serializes four data bits per pin for 2.5-D, or 3-D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of one cycle, energy efficiency of 77 fJ/b, and bandwidth density of 44…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658215
Publisher: IEEE

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A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing

A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing 150 150
Author(s): Jinhai Xiao, Yong Chen, Ningyi Zhang, Xiaolong Liu, Rui Liu, Junao Zhu, Chenghao Zhang, Peng Luo, Maliang Liu, Yintang Yang, Xiaohua Ma, Yue Hao

Abstract:

Cryogenic fractional- $N$ phase-locked loops (PLLs) are essential for large-scale superconducting quantum computing, and serve as integrated pump sources for Josephson parametric amplifiers. These PLLs enable high-fidelity qubit readout while reducing the thermal load and wiring complexity associated with room-temperature generators. However, the cryogenic pump sources developed thus far were …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653994
Publisher: IEEE

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Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS

Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS 150 150
Author(s): Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu K. Mathew

Abstract:

This work describes a side-channel attack (SCA)-resistant hash-based message authentication code (HMAC) accelerator with secure hash algorithm 2 (SHA-2) using Boolean and arithmetic masking along with the first-reported ASIC implementation in Intel 4 CMOS with 10 M measured traces. Previously reported masked datapath suffers from high area/performance overheads (>100%) designs due to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1026 – 1036
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3647096
Publisher: IEEE

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A Sub-Threshold Oscillator-Based High-Accuracy Temperature Sensor With Tolerance to Supply Fluctuation and Device Aging

A Sub-Threshold Oscillator-Based High-Accuracy Temperature Sensor With Tolerance to Supply Fluctuation and Device Aging 150 150
Author(s): Wei Wang, Yumin Su, Shayok Dutta, Liwen Jiang, Zhiyu Chen, Zhanghao Yu, Caleb Kemere, Kaiyuan Yang

Abstract:

Accurate, low-power, and compact temperature sensors are demanded in a wide range of biomedical, environmental, and industrial sensing applications. This article presents an accurate and precise CMOS temperature sensor based on a sub-threshold ring oscillator (RO) in 180 nm. The sensing core employs a five-stage super cut-off contention-free (SCCF) delay cell …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3644747
Publisher: IEEE

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A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer

A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer 150 150
Author(s): Zhengqi Xu, Zhiyuan Zhao, Michael A. Laun, Coleman DeLude, Justin Romberg, Michael P. Flynn

Abstract:

This article introduces a hybrid Slepian beamforming receiver architecture with low power and area costs. Traditional large-scale true-time-delay (TTD) beamformers for wideband wireless communication suffer from high power consumption and high hardware costs. As an alternative, the Slepian beamforming approach reduces the number of analog-to-digital conversions (ADCs) and delays for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651452
Publisher: IEEE

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A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue

A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue 150 150
Author(s): Alin Thomas Tharakan, Cong Huang, Yiheng Fu, Horacio Londoño Ramírez, Stéphanie P. Lacour, Mahsa Shoaran

Abstract:

This letter presents an 8-channel current-mode stimulator achieving a ±10.2 V voltage compliance in a standard CMOS process, supporting up to 4.5 mA stimulation current per channel. The proposed dynamic charge pump (DCP), which adaptively sizes its switches based on the stimulation current, helps achieve ~15% higher power efficiency at low currents compared …

Published in: IEEE Solid-State Circuits Letters
Page(s): 49 – 52
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3653014
Publisher: IEEE

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A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications 150 150
Author(s): Hsi-Hao Huang, Zong-Rui Cao, Ying-Ying Cheng, Jia-Yu Lin, Chen-Yi Lee

Abstract:

This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18- $\mu $ m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 41 – 44
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652323
Publisher: IEEE

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