Circuits

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24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS

24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS 150 150
Author(s): Cheng-Bin Chen, Tsung Chen, Yuan-Hao Huang

Abstract:

This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG …

Published in: IEEE Solid-State Circuits Letters
Page(s): 253 – 256
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3605369
Publisher: IEEE

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FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability

FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability 150 150
Author(s): Mohammad Khairul Bashar, T. H. Pantha, Z. Li, M. Farasat, S. Datta, V. Narayanan, S. Dutta, N. Shukla

Abstract:

In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 81 – 89
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3603942
Publisher: IEEE

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Polar-Axis Orientation Fluctuations and the Impact on the Intrinsic Variability in Ferroelectric Capacitors

Polar-Axis Orientation Fluctuations and the Impact on the Intrinsic Variability in Ferroelectric Capacitors 150 150
Author(s): Wei Zhang, Jianze Wang, Xuanyao Fong

Abstract:

We utilized phase-field simulations to investigate the effects of polar-axis (PA) orientation fluctuations on the extrinsic properties of single ferroelectric (FE) grains, focusing on the coercive electrical field (EC) and the remnant polarization (Pr). The underlying mechanisms through which PA orientation fluctuations influence polarization behavior are studied to gain insights …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 74 – 80
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3586589
Publisher: IEEE

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A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors

A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors 150 150
Author(s): Zikang Lin, Xiaohui Wu, Shujing Zhao, Weihua Liu, Xin Li, Li Geng, Chuanyu Han

Abstract:

In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 60 – 66
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3573709
Publisher: IEEE

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CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability

CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability 150 150
Author(s): Sufia Shahin, Swati Deshwal, Anirban Kar, Mahdi Benkhelifa, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 51 – 59
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3568622
Publisher: IEEE

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An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K

An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K 150 150
Author(s): Hafeez Raza, Shivendra Singh Parihar, Yogesh Singh Chauhan, Hussam Amrouch, Avinash Lahgere

Abstract:

In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage ( $V_{\min }$ ) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM $V_{\min }$ evaluation, we have measured the FinFETs fabricated using a commercial 5…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 42 – 50
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3560215
Publisher: IEEE

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Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 150 150
Author(s): Jianzi Jin, Shifan Gao, Cimang Lu, Xiang Qiu, Yi Zhao

Abstract:

A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 19 – 24
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3539470
Publisher: IEEE

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Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 150 150
Author(s): Yusaku Shiotsu, Satoshi Sugahara

Abstract:

A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 25 – 33
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3538702
Publisher: IEEE

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