Capacitors

An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control

An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control 150 150

Abstract:

A single-inductor multiple-output (SIMO) buck converter employing reordered power-distributive control (RPDC) is presented to achieve ultralow cross regulation. Adedicated power-distribution controller implements RPDC by adaptively adjusting the switching sequence: when the inductor current is insufficient, the switching period is extended, and when excessive, an end phase in the form of …

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A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter

A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter 150 150

Abstract:

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a $100~000{\times }$ input power dynamic range (DR) (from $10~{\mu }$ W to 1W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. …

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A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception

A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception 150 150

Abstract:

This letter presents a multiband fully integrated ultralow-power (ULP) transceiver with a two-step wake-up receiver (WuRX) and switched-capacitor (SC)-based high-efficiency transmitter. Operating from 200 MHz to 1 GHz, the transceiver covers most IoT applications on a single chip. By employing a novel two-step wake-up scheme with a rotating correlator, the proposed …

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PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC

PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC 150 150

Abstract:

Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, …

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A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants

A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants 150 150

Abstract:

Miniaturized biomedical implants are currently constrained by limited wireless power transfer (WPT) efficiency under load variation and spatial misalignment. This work presents a custom magnetoelectric (ME) power link incorporating a load-adaptive CMOS rectifier to address these challenges. By employing a current sensing control loop for dynamic switch sizing and delay …

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A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM

A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM 150 150

Abstract:

This article presents a noise-shaping successive approximation register (NS-SAR)-based direct-digitizing electrophysiological (ExG) sensing frontend (SFE) fabricated in a standard 180-nm CMOS process. To address the challenges of large motion artifacts and high electrode–tissue impedance (ETI), we propose three key innovations in our proposed SFE that enable accurate ExG …

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A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology

A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 150 150

Abstract:

This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. …

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

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A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988-μm Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications

A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988-μm Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications 150 150

Abstract:

This article presents a 3-Mpixel (Mp) three-stacked digital pixel sensor (DPS) featuring the world’s smallest pixel pitch of $2.988~\mu $ m, achieving a low temporal random noise (RN) of 1.16 e-rms and a high dynamic range (HDR) of 123 dB in global-shutter (GS) operation mode for versatile applications. To realize both the …

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