Capacitors

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery 150 150

Abstract:

This article presents a reconfigurable switched-capacitor (SC) DC–DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) …

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A Quadrature-Rotation Phased-Array Transmitter With High-Resolution Phase Tuning and Complex Domain Power Back-Off Efficiency Enhancement

A Quadrature-Rotation Phased-Array Transmitter With High-Resolution Phase Tuning and Complex Domain Power Back-Off Efficiency Enhancement 150 150

Abstract:

In this article, a four-element digital-modulated phased-array transmitter based on quadrature switched/floated-capacitor power amplifiers (SFCPAs) and reconfigurable switched-capacitor tuning lines (RSCTLs) is proposed. Phase shifting in each element is achieved by hybrid coarse and fine phase-tuning approaches. The SFCPAs with the quadrature-rotation technique are presented for coarse phase tuning. …

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A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset

A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset 150 150

Abstract:

This letter presents a capacitor-assisted transformer (CTF)-based voltage-controlled oscillator (VCO) that achieves a low flicker-noise corner with submilliwatt power consumption and compact chip area. By introducing a small assisting capacitor into the transformer, the higher order tank impedance is reshaped from the second-resonance region toward the third-resonance region, resulting …

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HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro

HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro 150 150

Abstract:

This letter presents HyFPCiM, a 65-nm FP8 compute-in-memory (CiM) macro that enables sub-mW floating-point (FP) inference using error-sensitivity-aware FP partitioning (EAP). EAP maps exponent processing to a digital CiM (DCiM) path and mantissa accumulation to an analog CiM (ACiM), avoiding the power- and area-intensive adder-tree-based accumulation used in prior FP-CiM …

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A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise 150 150

Abstract:

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To …

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A 10.1-ENOB 8kHz Bandwidth 95–250nW PVT-Robust DT Level-Crossing ADC for Sparse and Generic Signals

A 10.1-ENOB 8kHz Bandwidth 95–250nW PVT-Robust DT Level-Crossing ADC for Sparse and Generic Signals 150 150

Abstract:

This article presents an event-driven discrete-time level crossing analog-to-digital converter (DT-LCADC) that is energy-efficient in converting both sparse and generic signals and is robust against process voltage and temperature (PVT) variations. The proposed DT-LCADC uses the comparator delay to classify each level-crossing event as slow (produced by a small input …

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A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM

A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM 150 150

Abstract:

Computing-in-memory (CIM) is a promising paradigm for energy- and area-efficient implementation of the heavy general matrix multiplication (GEMM) operations, especially in the evolving deep learning algorithms. Though existing CIM macros have demonstrated remarkable energy/area efficiency, the corresponding metrics of the system-level CIM chips degrade due to the peripheral components, …

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A MEMS-Free 4096-Pixel CMOS E-Nose Array With MOF-Based Molecular Selectivity, In-Pixel Thermal Regeneration, and a Compact Single-Coefficient Bandpass Sigma–Delta ADC

A MEMS-Free 4096-Pixel CMOS E-Nose Array With MOF-Based Molecular Selectivity, In-Pixel Thermal Regeneration, and a Compact Single-Coefficient Bandpass Sigma–Delta ADC 150 150

Abstract:

This work presents a CMOS-only [micro-electromechanical systems (MEMS)-free] electronic nose (e-nose) for concurrent multi-gas-sensing applications. The proposed system integrates 4096 capacitance-to-digital converter (CDC) pixels, each implementing a compact bandpass sigma–delta ( $\Sigma \Delta $ ) ADC with a single feedback coefficient and no additional feedforward or feedback paths, achieving each pixel footprint …

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An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique

An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique 150 150

Abstract:

This article presents a discrete-time, third-order, single-loop, 17-level delta-sigma modulator (DSM) for high-dynamic-range sensor measurement applications, which employs a loop filter auto-shift (LFAS) technique. It uses an on-chip 1.5-bit Schmitt monitor to determine whether the input amplitude is large or small. The DSM automatically shifts to loop filter A for …

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