Analog-to-digital converter (ADC)

  • No Comments

A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression

A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression 150 150
Author(s): Yuzhou Xiong, Guolong Fu, Xianghui Zhang, Shian Wang, Yuke Shen, Yuhua Liang, Zhong Tang, Yanbo Zhang, Zhangming Zhu

Abstract:

This article presents a multi-rate successive approximation register (SAR)-assisted exponential-incremental (EI) pipeline analog-to-digital converter (ADC) for wireless communication applications. By employing a multi-rate scheme, the ADC harnesses the benefits of oversampling and noise-shaping (NS) techniques while avoiding bandwidth (BW) degradation. To further increase the BW to hundreds of megahertz …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733687
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique

A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique 150 150
Author(s): Linran Zhao, Yiming Han, Yaoyao Jia

Abstract:

This article presents a low-power continuous-time (CT) $G_{mathrm {M}}$ -C-based $Delta Sigma $ analog-to-digital converter (ADC) employing capacitive input feedforward and a duty-cycled $G_{mathrm {M}}$ technique to enhance linearity while maintaining high energy efficiency. The ADC employs a CT capacitive network for concurrent signal summation and quantization, enabling input …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733305
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification 150 150
Author(s): Hongjiang Chen, Jingxiang Wang, Kaize Zhang, Shizhan Mo, Liang Qi, Chao Zhao, Hao Zhang, Zhang Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730470
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration 150 150
Author(s): Tohru Kaneko, Hideaki Ishida, Yuzuru Yamaki, Satoshi Takehara, Un-Ku Moon

Abstract:

This article summarizes a calibration-free, frequency-scalable $Delta Sigma $ analog-to-digital converter (ADC) which employs dynamic open-loop integrators for low-power sensing systems. The integrators use a capacitive degeneration scheme to obtain an integration factor determined by a capacitor ratio. To enhance process-voltage-temperature (PVT) robustness, bottom-plate level shift (BPLS) and a timer are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719645
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter 150 150
Author(s): Chaoyang Xing, Yilu Cui, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This article presents a continuous-time (CT) analog-to-digital converter (ADC) featuring an incremental zoom with extended quantization architecture. The proposed MASH topology comprises an 8-bit oversampled successive-approximation register (SAR) ADC as the first stage, a 1-bit incremental CT delta-sigma modulator (CT-DSM) as the second stage, and a 12-bit Nyquist SAR ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717666
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer

A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer 150 150
Author(s): Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This work presents a pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a current-buffer-based integrating sampler that combines an easy-to-drive resistive input with high linearity. To overcome the linearity and swing limitations of conventional current-integrating samplers (CISs), the frontend employs a $G_{m}$ -boosted continuous-time (CT) floating charge transferrer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714848
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 150 150
Author(s): Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin D. Patino-Sosa, Philip Anschutz, Amanda Jacob, Keshav Ramachandra, Samuel Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe

Abstract:

This article presents a 32-channel time-multiplexed highly digital neural recording front-end (RFE) that exhibits sub- $8.8~\mu $ s recovery latency from large stimulation artifacts while delivering high-resolution data at the Nyquist rate. The RFE is time-shared across 32 channels for low-frequency electrocorticography (ECoG) recording and across four channels for high-frequency action potentials (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1053 – 1067
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3643367
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique 150 150
Author(s): Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang

Abstract:

This article presents an incremental noise-shaping (NS) pipeline analog-to-digital converter (ADC) featuring a single-amplification-based kT/C noise cancellation technique. By pre-amplifying the frontend sampling kT/C noise onto the capacitive digital-to-analog converter (CDAC) of the backend NS successive approximation register (SAR) quantizer, the proposed architecture eliminates the repeated amplifications typically …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698875
Publisher: IEEE

View on IEEE Xplore

Search this website