Special Issue on Chiplet Interconnect and Architectures

Chiplet-based architectures and die-to-die interconnect technologies are increasingly critical for scaling the performance, power efficiency, and overall capabilities of integrated circuits. With traditional monolithic scaling slowing, chiplet-based designs and advanced integration techniques offer significant advantages, enabling high-density, energy-efficient, and high-performance solutions. Technologies such as 2.5D integration using silicon interposers, advanced side-by-side die-to-die interconnect interfaces, hybrid bonding, systems-on-wafer, co-packaged optics, and 3D stacking strategies are rapidly evolving, driving innovation in chiplet-based architectures across various applications, including data centers, AI accelerators, edge computing, and beyond.

This special issue aims to explore the latest advances, challenges, and opportunities in chiplet interconnects and their implications for system-level integration. Original research articles detailing novel integrated circuits and architectures, as well as comprehensive review articles highlighting key developments and future trends, are strongly encouraged.

Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the scope of this special issue. Topics include (but are not limited to):

• High-density and low-latency die-to-die interconnect technologies
• Advanced side-by-side chiplet interfaces and silicon interposers
• Hybrid bonding technologies and their applications
• 2.5D integration and silicon interposer technologies
• Innovative 3D stacking techniques and architectures
• Energy-efficient signaling circuits for chiplet communication
• System-level innovations enabled by chiplet-based integration
• Wafer-level, panel-level chiplet systems, and integrated photonics
• Design and testing methodologies and tools for 2.5D and 3D integration

All submitted manuscripts are strongly encouraged to:

1. conform to OJ-SSCS’ normal formatting requirements and page count limits;
2. validate principal claims with experimental results;
3. be submitted online at: https://ieee.atyponrex.com/submission/dashboard?siteName=oj-sscs

Please note that you need to select “Chiplet Interconnect and Architectures” when you submit a paper to this Special Issue.

• Special Section Open for Submissions: April 1, 2025
• Paper Submission Deadline: June 24, 2025
• First Notification: July 31, 2025
• Revision Submission: August 31, 2025
• Final Decision: October 15, 2025
• Publication Online: November 8, 2025

Shenggao Li, TSMC, San Jose, USA
Tony Chan Carusone, Alphawave Semi and University of Toronto, Toronto, Canada