IEEE Journal of Solid-State Circuits (JSSC)
Jan Craninckx
JSSC Editor-in-Chief
The most recent
top 50 downloaded articles
Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
Subscribe to the journal
Add to my alerts to sign-up for JSSC e-mail alerts
Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, an mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page count does not include reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- High-Efficiency Millimeter-Wave Single-Ended and Differential Fundamental Oscillators in CMOS
- A High-Fractional-Bandwidth, Millimeter-Wave Bidirectional Image-Selection Architecture With Narrowband LO Tuning Requirements
- Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators
- Analysis and Design of Commutation-Based Circulator-Receivers for Integrated Full-Duplex Wireless
- Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations
- An 80-Gb/s 44-mW Wireline PAM4 Transmitter
- A Wirelessly Powered UWB RFID Sensor Tag With Time-Domain Analog-to-Information Interface
- Oversampling Successive Approximation Technique for MEMS Differential Capacitive Sensor
- An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback
- Toward Temperature Tracking With Unipolar Metal-Oxide Thin-Film SAR C-2C ADC on Plastic
- A 19.8-mW Eddy-Current Displacement Sensor Interface With Sub-Nanometer Resolution
- A Front-End ASIC With High-Voltage Transmit Switching and Receive Digitization for 3-D Forward-Looking Intravascular Ultrasound Imaging
- A 22 V Compliant 56
${mu}$ - A 1.08-nW/kHz 13.2-ppm/C Self-Biased Timer Using Temperature-Insensitive Resistive Current
- A Time-Resolved Four-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy
- A 65-nm CMOS Low Dropout Regulator Featuring 60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range
- An AC Input Inductor-Less LED Driver for Efficient Lighting and Visible Light Communication
- A 1.24
$mu$ - A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices
- A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
- A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
- Integration Trends in Monolithic Power ICs: Application and Technology Challenges
- A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS
- A 5.6 nV/Hz Chopper Operational Amplifier Achieving a 0.5 V Maximum Offset Over Rail-to-Rail Input Range with Adaptive Clock Boosting Technique
- A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3 DC-to-RF Efficiency, and 1-GHz Divided-Down Output
- Short Regular Papers A Multi-Gigabit CPFSK Polymer Microwave Fiber Communication Link in 40 nm CMOS
- Design and Analysis of Chopper Stabilized Injection-Locked Oscillator Sensors Employing Near-Field Modulation
- A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
- A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
- Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a 5 x 6 Vpp Chip-to-Chip Bondwire Output to an MZM PIC
- A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
- A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
- A Novel 100 MHz-45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15 m GaN-SiC Wafer Process Technology
- An Interface ASIC for MEMS Vibratory Gyroscopes With a Power of 1.6 mW, 92 dB DR and 0.007
- A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM
- A NMR CMOS Transceiver Using a Butterfly-Coil Input for Integration with a Digital Microfluidic Device inside a Portable Magnet
- An RC Oscillator With Comparator Offset Cancellation
- A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement
- A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar