IEEE Journal of Solid-State Circuits (JSSC)
Jan Craninckx
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
New Submission Template and Manuscript Length Instructions
To ease editing and reviewing in electronic format, manuscripts have to be submitted following the two-column format as used for all IEEE Transactions.
Regular papers are allowed to have up to 8 pages in this two-column format. This page limit is valid for the whole manuscript, but excluding references and bios. All figures must be sized such that they are properly readable and placed inline at their relevant position in the text. No modifications to the IEEE templates are allowed.
Exceptions of up to 4 extra pages are possible for systems or topics that do not fit in this regular length. To request such an exception, a detailed motivation must be provided at the time of submission. Exceptions are subject to approval by the editorial board.
More information for authors is available here.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Wideband Dual-Injection Path Self-Interference Cancellation Architecture for Full-Duplex Transceivers
- A Reconfigurable Architecture Using a Flexible LO Modulator to Unify High-Sensitivity Signal Reception and Compressed-Sampling Wideband Signal Detection
- Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor
- A Chopping Switched-Capacitor RF Receiver With Integrated Blocker Detection
- A 0.18-V 382-
$mu$ - Design of 1.8-mW PLL-Free 2.4-GHz Receiver Utilizing Temperature-Compensated FBAR Resonator
- A Near-Zero-Power Wake-Up Receiver Achieving 69-dBm Sensitivity
- A 500-MHz Bandwidth 7.5-mVpp Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters
- Split-Array, C-2C Switched-Capacitor Power Amplifiers
- Power-Efficient
$W$ - A Self-Tuning Resonant-Inductive-Link Transmit Driver Using Quadrature Symmetric Delay Trimmable Phase-Switched Fractional Capacitance
- A 2.4-GHz RF Fractional-
${N}$ $= 0.25f_{mathrm{ REF}}$ - Digital Fractional-
$N$ - 0.04-mm2 103-dB-A Dynamic Range Second-Order VCO-Based Audio
$SigmaDelta$ $mu$ - A Bypass-Switching SAR ADC With a Dynamic Proximity Comparator for Biomedical Applications
- A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction
- A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation
- An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching
- 1.23-pJ/bit 25-Gb/s Inductor-Less Optical Receiver With Low-Voltage Silicon Photodetector
- A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
- A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
- Integration Trends in Monolithic Power ICs: Application and Technology Challenges
- A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS
- A 5.6 nV/Hz Chopper Operational Amplifier Achieving a 0.5 V Maximum Offset Over Rail-to-Rail Input Range with Adaptive Clock Boosting Technique
- A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3 DC-to-RF Efficiency, and 1-GHz Divided-Down Output
- Short Regular Papers A Multi-Gigabit CPFSK Polymer Microwave Fiber Communication Link in 40 nm CMOS
- Design and Analysis of Chopper Stabilized Injection-Locked Oscillator Sensors Employing Near-Field Modulation
- A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
- A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
- Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a 5 x 6 Vpp Chip-to-Chip Bondwire Output to an MZM PIC
- A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
- A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
- A Novel 100 MHz-45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15 m GaN-SiC Wafer Process Technology
- An Interface ASIC for MEMS Vibratory Gyroscopes With a Power of 1.6 mW, 92 dB DR and 0.007
- A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM
- A NMR CMOS Transceiver Using a Butterfly-Coil Input for Integration with a Digital Microfluidic Device inside a Portable Magnet
- An RC Oscillator With Comparator Offset Cancellation
- A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement
- A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar