IEEE Journal of Solid-State Circuits (JSSC)
Pavan Kumar Hanumolu
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium
- A 2534-GHz Eight-Element MIMO Transmitter for Keyless High Throughput Directionally Secure Communication
- A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control
- Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs
- A Multi-Band 1652-GHz Transmit Phased Array Employing 4 1 Beamforming IC With 1415.4-dBm
P sat for 5G NR FR2 Operation - High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation
- Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS
- Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions
- High Efficiency
D -Band Multiway Power Combined Amplifiers With 17.519-dBm Psat and 14.212.1 Peak PAE in 45-nm CMOS RFSOI - A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping
- A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS
- A Sub-100 Fs RMSjitter 20 GHz Fractional-
N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference - Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation
- A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7
Arms Input Noise in 22 nm FinFET CMOS - A Sub-100-W 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS
- Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging
- A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving 44-dBc HD3 Up To 1.5-Vp-p Output Swing Over 0.015.4-GHz for Direct RF Sampling Applications
- A Wideband IQ-Mapping Direct-Digital RF Modulator for 5G Transmitters
- A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation
- Design of an amplitude-stable sine-wave oscillator
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- New techniques for drift compensation in integrated differential amplifiers
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate
- A noise cancellation technique in active RF-CMOS mixers
- 20-Mb/s erase/record flash memory by asymmetrical operation
- A mixed EFL/I/sup 2/L digital telecommunication integrated circuit
- A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
- Metastability of CMOS latch/flip-flop
- Synthesis of operational amplifiers