IEEE Journal of Solid-State Circuits (JSSC)
Pavan Kumar Hanumolu
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC)
- A VHF Wide-Input Range CMOS Passive Rectifier With Active Bias Tuning
- Stacking Isolated SC Cores for High-Voltage Wide Input Range Monolithic DCDC Conversion
- Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH DeltaSigma Modulator
- A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability
- Processor EnergyPerformance Range Extension Beyond Voltage Scaling via Drop-In Methodologies
- A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation
- An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for
In Situ Personalization on Smart Devices - A 390-GHz Outphasing Transmitter in 28-nm CMOS
- A 20-GHz 1.9-mW LNA Using
g m-Boost and Current-Reuse Techniques in 65-nm CMOS for Satellite Communications - A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth
- A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
- Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
- A 12.3-W 0.72-mm Fully Integrated Front-End IC for Arterial Pulse Waveform and ExG Recording
- A 15-Channel Orthogonal Code Chopping Instrumentation Amplifier for Area-Efficient, Low-Mismatch Bio-Signal Acquisition
- Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability
- A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors
- Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing
- A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter
- Correction to "A CMOS Voltage Reference"
- Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
- Design of an amplitude-stable sine-wave oscillator
- Correction to "high-Q Hf microelectromechanical filters"
- Authors' Reply
- Correction to "Minimum Propagation Delays in VLSI"
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate