IEEE Journal of Solid-State Circuits (JSSC)
Dennis Sylvester
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- New Associate Editor
- New Associate Editor
- Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium
- A 0.4-4 THz p-i-n Diode Frequency Multiplier in 90-nm SiGe BiCMOS
- 280-GHz Frequency Multiplier Chains in 250-nm InP HBT Technology
- A 117.5–155-GHz SiGe ×12 Frequency Multiplier Chain With Push-Push Doublers and a Gilbert Cell-Based Tripler
- A Ka-Band InP HBT MMIC Power Amplifier With 19.8:1 IP3/Pdc LFOM at 48 GHz
- A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator
- A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
- Design Aspects of Single-Ended and Differential SiGe Low-Noise Amplifiers Operating Above fmax/2in Sub-THz/THz Frequencies
- A Wideband Digital-Intensive Current-Mode Transmitter Line-Up
- A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range
- A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise
- A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion
- A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K2 Resolution FoM in 65-nm CMOS
- A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization
- A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier
- A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC
- A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 °C to 165 °C Consuming 210 μW at 70 MHz
- Design of an amplitude-stable sine-wave oscillator
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- New techniques for drift compensation in integrated differential amplifiers
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate
- A noise cancellation technique in active RF-CMOS mixers
- 20-Mb/s erase/record flash memory by asymmetrical operation
- A mixed EFL/I/sup 2/L digital telecommunication integrated circuit
- A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
- Metastability of CMOS latch/flip-flop
- Synthesis of operational amplifiers