IEEE Journal of Solid-State Circuits (JSSC)
Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits
- Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter
- A 200-
W Interface for High-Resolution Eddy-Current Displacement Sensors
- A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation
- A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring
- An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
- A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS
- Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
- RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator
- Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition
- A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage
- A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
- MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices
- A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon Processor
- A High-Linearity and Low-EMI Multilevel Class-D Amplifier
- An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques
- A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3
Inaccuracy of 0.02, 0.12 for Battery-Monitoring Applications
- A 440-W, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
- An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS
- Correction to "A CMOS Voltage Reference"
- Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
- Design of an amplitude-stable sine-wave oscillator
- Correction to "high-Q Hf microelectromechanical filters"
- Authors' Reply
- Correction to "Minimum Propagation Delays in VLSI"
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate