IEEE Journal of Solid-State Circuits (JSSC)
Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)
- A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
- A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control
- 10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture
- A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-
NMDLL in 22-nm FinFET CMOS
- A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique
- NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics
- IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
- Cores, Cache, Content, and Characterization: IBMs Second Generation 14-nm Product, z15
- A 1.5-
J/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots
- A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing
- EM and Power SCA-Resilient AES-256 Through 350 Current-Domain Signature Attenuation and Local Lower Metal Routing
- A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS
- STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete SpinSpin Interactions
- A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-
- A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
- A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
- An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
- A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg 75
s and tR 4 s
- Correction to "A CMOS Voltage Reference"
- Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
- Design of an amplitude-stable sine-wave oscillator
- Correction to "high-Q Hf microelectromechanical filters"
- Authors' Reply
- Correction to "Minimum Propagation Delays in VLSI"
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate