IEEE Journal of Solid-State Circuits (JSSC)

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The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.

Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.

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The most recent top 50 downloaded articles.

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Boris Murmann

JSSC Editor-in-Chief

JSSC Papers on IEEE Xplore

Latest Issue

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A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

 A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique 150 150

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

 A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations 150 150

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

 A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

 A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression 150 150

MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator

 MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator 150 150

A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control

 A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control 150 150

Single-X-Ray Sensitive Energy-Binning Dosimeter for Closed-Loop Cancer External-Beam Radiotherapy

 Single-X-Ray Sensitive Energy-Binning Dosimeter for Closed-Loop Cancer External-Beam Radiotherapy 150 150

A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

 A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface 150 150

A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation

 A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation 150 150

Early Access

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AFP-CIM: All-Inclusive Floating-Point With Segmented Compute-in-Memory Macro

 AFP-CIM: All-Inclusive Floating-Point With Segmented Compute-in-Memory Macro 150 150

An Efficient Power Management Unit With Continuous MPPT and Energy Recycling for Wireless Millimetric Biomedical Implants

 An Efficient Power Management Unit With Continuous MPPT and Energy Recycling for Wireless Millimetric Biomedical Implants 150 150

A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing

 A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing 150 150

A 3 × 3 Multi-Chip Ka-Band Phased Array With 2-D-Scalable LO Distribution and Phase Self-Alignment

 A 3 × 3 Multi-Chip Ka-Band Phased Array With 2-D-Scalable LO Distribution and Phase Self-Alignment 150 150

A Real-Time Deep Reinforcement Learning Processor for Mapless Autonomous Navigation With Unified Actor-Critic Network and Inference-on-Request Scheduling

 A Real-Time Deep Reinforcement Learning Processor for Mapless Autonomous Navigation With Unified Actor-Critic Network and Inference-on-Request Scheduling 150 150

A Hybrid SCVR With 4 × C F Continuously Scalable-Conversion Ratio SC Stage

 A Hybrid SCVR With 4 × C F Continuously Scalable-Conversion Ratio SC Stage 150 150

A 22.4–25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction

 A 22.4–25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction 150 150

Design of G-Band Watt-Level GaN Power Amplifier With Multiband Large-Signal Impedance Correction and Circuit-Package Co-Design Technique

 Design of G-Band Watt-Level GaN Power Amplifier With Multiband Large-Signal Impedance Correction and Circuit-Package Co-Design Technique 150 150

A Segment-Interlace Multi-Phase Hybrid Converter With Concurrent Inductor Energizing and Inherent Current Balancing

 A Segment-Interlace Multi-Phase Hybrid Converter With Concurrent Inductor Energizing and Inherent Current Balancing 150 150
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