IEEE Journal of Solid-State Circuits (JSSC)
Jan Craninckx
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, an mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page count does not include reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC)
- A 6.9-
$mu$ - A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240
$times$ - Personal Inertial Navigation System Assisted by MEMS Ground Reaction Sensor Array and Interface ASIC for GPS-Denied Environment
- A Pitch-Matched Front-End ASIC With Integrated Subarray Beamforming ADC for Miniature 3-D Ultrasound Probes
- Design and Implementation of Reference-Free Drift-Cancelling CMOS Magnetic Sensors for Biosensing Applications
- A Multimodal CMOS MEA for High-Throughput Intracellular Action Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications
- A 0.13-
$mutext{m}$ - Sub-
$mu$ $mu$ - Fully Immersible Subcortical Neural Probes With Modular Architecture and a Delta-Sigma ADC Integrated Under Each Electrode for Parallel Readout of 144 Recording Sites
- A 0.3-V CMOS Biofuel-Cell-Powered Wireless Glucose/Lactate Biosensing System
- A Fully Configurable Non-Linear Mixed-Signal Interface for Multi-Sensor Analytics
- NURIP: Neural Interface Processor for Brain-State Classification and Programmable-Waveform Neurostimulation
- A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training
- A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor
- Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration
- Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering
- A 27-GHz Quad-Core CMOS Oscillator With No Mode Ambiguity
- Second-Harmonic Power Generation Limits in Harmonic Oscillators
- A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
- A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
- Integration Trends in Monolithic Power ICs: Application and Technology Challenges
- A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS
- A 5.6 nV/Hz Chopper Operational Amplifier Achieving a 0.5 V Maximum Offset Over Rail-to-Rail Input Range with Adaptive Clock Boosting Technique
- A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3 DC-to-RF Efficiency, and 1-GHz Divided-Down Output
- Short Regular Papers A Multi-Gigabit CPFSK Polymer Microwave Fiber Communication Link in 40 nm CMOS
- Design and Analysis of Chopper Stabilized Injection-Locked Oscillator Sensors Employing Near-Field Modulation
- A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
- A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
- Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a 5 x 6 Vpp Chip-to-Chip Bondwire Output to an MZM PIC
- A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
- A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
- A Novel 100 MHz-45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15 m GaN-SiC Wafer Process Technology
- An Interface ASIC for MEMS Vibratory Gyroscopes With a Power of 1.6 mW, 92 dB DR and 0.007
- A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM
- A NMR CMOS Transceiver Using a Butterfly-Coil Input for Integration with a Digital Microfluidic Device inside a Portable Magnet
- An RC Oscillator With Comparator Offset Cancellation
- A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement
- A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar