IEEE Journal of Solid-State Circuits (JSSC)
Dennis Sylvester
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE Journal of Solid-State Circuits Publication Information
- Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC)
- An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop
- A BJT-Based Temperature-to-Frequency Converter With 1C (3) Inaccuracy From 40 C to 140 C for On-Chip Thermal Monitoring
- Arithmetic Progression Switched-Capacitor DCDC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery
- Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators
- FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems
- A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and
V /T Variation-Tolerant Low-Cost IoT Security - High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm
- A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration
- A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface
- A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation
- Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
- A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS
- An Ultrasound ASIC With Universal Energy Recycling for 7-m All-Weather Metamorphic Robotic Vision
- A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF
- An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves
- A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ADC for Saturation-Free Closed-Loop Neural Interfaces
- A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer
- A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier
- Design of an amplitude-stable sine-wave oscillator
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- New techniques for drift compensation in integrated differential amplifiers
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate
- A noise cancellation technique in active RF-CMOS mixers
- 20-Mb/s erase/record flash memory by asymmetrical operation
- A mixed EFL/I/sup 2/L digital telecommunication integrated circuit
- A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
- Metastability of CMOS latch/flip-flop
- Synthesis of operational amplifiers