IEEE Journal of Solid-State Circuits (JSSC)
Pavan Kumar Hanumolu
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits
- A CMOS Temperature Stabilized 2-D Mechanical Stress Sensor With 11-bit Resolution
- A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna
- Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-
$mu$ - A Time Domain Artificial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition
- A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7-
$mu$ - A 640
$times$ - Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM
- A 0.32128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
- A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse MatrixMatrix Multiplication Accelerator
- A 4900-
$mu$ - A 7-nm 4-GHz Arm-Core-Based CoWoS Chiplet Design for High-Performance Computing
- Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW
- A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response
- Direct 48-/1-V GaN-Based DCDC Power Converter With Double Step-Down Architecture and MasterSlave AO2T Control
- A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique
- An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
- A Continuous-Time Zoom ADC for Low-Power Audio Applications
- A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping
- Correction to "A CMOS Voltage Reference"
- Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
- Design of an amplitude-stable sine-wave oscillator
- Correction to "high-Q Hf microelectromechanical filters"
- Authors' Reply
- Correction to "Minimum Propagation Delays in VLSI"
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate