IEEE Journal of Solid-State Circuits (JSSC)
Dennis Sylvester
JSSC Editor-in-Chief
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Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
For all questions or information on the submission process, please visit our information for authors page or contact jsscadmin@ieee.org
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- New Associate Editor
- Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium
- A 28 nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter With On-Chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices
- A Broadband Four-Way Parallel–Series Doherty Power Amplifier for 5G Communications
- A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers
- A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive
- Compact mm-Wave Ultra-Wideband and Low-Noise Phase Alternately Distributed Quasi-Circulators
- A 10.8–14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration
- A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control
- A 400-GHz Efficient Radiator and OOK Transceiver for Multi-Gb/s Wireless Communication in Silicon
- Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS
- A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links
- A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond
- A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing
- RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback
- A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing
- A Monolithically Integrable Reconfigurable Antenna Based on Large-Area Electronics
- A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range
- A Simultaneous Energy Transferring SIBO Converter Achieving Low Ripple and High Efficiency for AMOLED Applications
- Design of an amplitude-stable sine-wave oscillator
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- New techniques for drift compensation in integrated differential amplifiers
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate
- A noise cancellation technique in active RF-CMOS mixers
- 20-Mb/s erase/record flash memory by asymmetrical operation
- A mixed EFL/I/sup 2/L digital telecommunication integrated circuit
- A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
- Metastability of CMOS latch/flip-flop
- Synthesis of operational amplifiers