IEEE Journal of Solid-State Circuits (JSSC)
Aims and Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.
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Information for Authors:
- "How to write a JSSC paper" presentation by Bram Nauta.
Introducing Overlength Page Charges
The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family
Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.
JSSC Papers on IEEE Xplore:
- A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application
- Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS
- A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications
- An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
- Integrated Self-Adaptive and Power-Scalable Wideband Interference Cancellation for Full-Duplex MIMO Wireless
- A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement
- Design of a 0.6-V, 429-MHz FSK Transceiver Using Q-Enhanced and Direct Power Transfer Techniques in 90-nm CMOS
- A Batteryless Motion-Adaptive Heartbeat Detection System-on-Chip Powered by Human Body Heat
- A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration
- An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs
- A Low-Power VGA Vision Sensor With Embedded Event Detection for Outdoor Edge Applications
- Breaking the Performance Tradeoffs in N-Path Mixer-First Receivers Using a Second-Order Baseband Noise-Canceling TIA
- An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation ASIC
- A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ADCs
- An Automotive LiDAR SoC for 240 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE
- A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons
- A 6.5-
W 10-kHz BW 80.4-dB SNDR Gm-C-Based CT Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording
- A Millimeter-Scale Single Charged Particle Dosimeter for Cancer Radiotherapy
- Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic Drug Monitoring
- Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression
- Correction to "A CMOS Voltage Reference"
- Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
- Design of an amplitude-stable sine-wave oscillator
- Correction to "high-Q Hf microelectromechanical filters"
- Authors' Reply
- Correction to "Minimum Propagation Delays in VLSI"
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Leak-compensated analog memory with pair mosfets
- CMOS analog front end of a transceiver with digital echo cancellation for ISDN
- Microwave CMOS-device physics and design
- Silicon-gate CMOS frequency divider for electronic wrist watch
- Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
- A CMOS VLSI chip for filtering of TV pictures in two dimensions
- A CMOS 0.8-/spl mu/m transistor-only 1.63-MHz switched-current bandpass /spl Sigma//spl Delta/ modulator for AM signal A/D conversion
- VLSI in consumer electronics
- Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
- MOVE Architecture in Digital Controllers
- A fully integrated CMOS DCS-1800 frequency synthesizer
- Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
- Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate