IEEE Fellows Program
The IEEE Grade of Fellow is conferred by the Board of Directors upon a person with an extraordinary record of accomplishments in any of the IEEE fields of interest. A brief citation is issued to new Fellows describing their accomplishments and the total number selected in any one year does not exceed one-tenth of one percent of the total voting Institute membership. Complete Program Information about the IEEE Fellows Program may be found here. The Fellow Nomination Process is described here. A Senior member can be nominated in one of four categories: application engineer/practitioner, educator, research engineer/scientist or technical leader.
The full list of Solid-State Circuits Society Members who are IEEE Fellows are listed here.
SSCS Members Elevated to Fellow in 2018
Pamela Ann Abshire
For contributions to CMOS biosensors
For contributions to integrated circuits for active medical devices
Andreas Demosthenous (S’94–M’99–SM’05–F’18) received the B.Eng. degree in electrical and electronic engineering from the University of Leicester, Leicester, U.K., the M.Sc. degree in telecommunications technology from Aston University, Birmingham, U.K., and the Ph.D. degree in electronic and electrical engineering from University College London (UCL), London, U.K., in 1992, 1994, and 1998, respectively. He is a Professor in the UCL Department of Electronic and Electrical Engineering and leads the Analog and Biomedical Electronics Group. His research interests include analog and mixed-signal integrated circuits for biomedical, sensor, and signal processing applications. He has made outstanding contributions to improving safety and performance in integrated circuit design for active medical devices, such as spinal cord and brain stimulators. He has authored over 300 articles in journals and international conference proceedings, several book chapters, and holds several patents.
He is currently the Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, an Associate Editor of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, and serves on the International Advisory Board of Physiological Measurement. He is a member of the Technical Programme Committee of several IEEE conferences, including the European Solid-State Circuits Conference and the International Symposium on Circuits and Systems.
Dr. Demosthenous is a fellow of the Institution of Engineering and Technology and a Chartered Engineer.
For contributions to energy-efficient and robust computing systems design
Saibal Mukhopadhyay (S’99–M’07–SM’11-F’18) received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Kolkata, India, and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2000 and 2006, respectively. He is currently a Professor with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. His research interests include design of energy-efficient, intelligent, and secure systems. His research explores a cross-cutting approach to design spanning algorithm, architecture, circuits, and emerging technologies.
Dr. Mukhopadhyay was a recipient of the Office of Naval Research Young Investigator Award in 2012, the National Science Foundation CAREER Award in 2011, the IBM Faculty Partnership Award in 2009 and 2010, the SRC Inventor Recognition Award in 2008, the SRC Technical Excellence Award in 2005, the IBM PhD Fellowship Award for years 2004 to 2005. He has received IEEE Transactions on VLSI Best Paper Award (2014), IEEE Transactions on Component, Packaging, and Manufacturing Technology Best Paper Award (2014), and multiple best paper awards in International Symposium on Low-power Electronics and Design (2014, 2015, and 2016). He has authored or co-authored over 200 papers in refereed journals and conferences, and holds five U.S. patents. Dr. Mukhopadhyay is a Fellow of IEEE.
Indian Institute of Technology
For contributions to delta sigma modulators and analog filters
Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. He is now a Professor of Electrical Engineering at the Indian Institute of Technology-Madras. Dr. Pavan is the recipient of several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009), the Shanti Swarup Bhatnagar Award from the Government of India (2012). He has been the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I - Regular Papers (2014-2015),and a Distinguished Lecturer of the IEEE Solid State Circuits Society. He is the author of Understanding Delta-Sigma Modulators (2nd Edition, with Richard Schreier and Gabor Temes), and a distingushed lecturer of the IEEE Circuits and Systems society (2018-2019). He is a fellow of the Indian National Academy of Engineering (INAE) and the Institute of Electrical and Electronic Engineers (IEEE).
For contributions to ultra low-power biomedical electronics
For contributions to variation-aware design and analysis of integrated circuits
Hidetoshi Onodera received BS, MS and PhD degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983, and currently a Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability. Dr. Onodera served as a Program Chair and a General Chair of ICCAD and ASP-DAC. He was a Chairman of SSCS Kansai Chapter, IEEE CASS Kansai Chapter, IEEE Kansai Section, IPSJ SIG-SLDM System LSI Design Methodology), and IEICE Technical Group on VLSI Design Technologies. He served as an Editor-in-Chief of IEICE Transactions on Electronics and IPSJ Transactions on System LSI Design methodology.
San Diego, CA, USA
For leadership in the development of silicon-on-sapphire technology
Isaac Lagnado, PhD, from San Diego, California, USA has been named an IEEE Fellow. Isaac has been an outstanding visionary in the area of integrated microelectronics virtually since its inception. In multiple cases, Isaac has put forward a vision of what could be achieved in a given technical area, years before it became perceived by others or popular. He has also assembled resources and personnel to pursue these visions, and guided the technologies through the initial R&D phase (covering materials and process development along with evolving circuit and system requirements). Perhaps the most prescient of Isaac's visions was to understand, demonstrate and publish the path for development of integrated circuits overall, in his February 1961 paper “Integrated Circuits Using a Semiconductor Element”, published in French. These very early contributions have been essentially overlooked in subsequent technical and historical accounts of the appearance of ICs. Within the US Navy, Isaac Lagnado was a strong proponent for, and led the way in investment for, advanced IC technologies including CMOS (beginning in 1970, well before its importance was evident in commercial applications), and sub-micron technology (his efforts within the Navy during 1973-1975 were the precursor for the US DoD sponsored VHSIC program 4-5 years later).
Isaac Lagnado has been one of the most pivotal persons in the evolution of silicon-on-insulator (initially silicon-on-sapphire, SOS) technology, for space, cell phones and other communication systems. The technology was successfully transferred to Peregrine Semiconductor (led by Ron Reedy, who came from the Navy effort).
Isaac Lagnado, upon his elevation to IEEE Fellow received the following citation: for leadership in envisioning, guiding and developing integrated circuit technologies, particularly silicon-on-sapphire technology.
Arizona State University – Tempe
Scottsdale, AZ, USA
For contributions to radio frequency circuits
Dr. Bakkaloglu received his PhD from Oregon State University in 1995 and joined Texas Instruments Inc. Mixed Signal Wireless Design Group, Dallas, TX, where he worked on analog, mixed-signal and RF front ends for wireless and wireline communication ICs. He was a design lead for system-on-chip designs with integrated power management and RF, analog baseband functionality as a design leader. In 2004 he joined the Electrical Engineering Department at Arizona State University, Tempe, AZ, as an associate professor. His research interests include mixed-signal circuit design for integrated supply regulators, biomedical, chemical and MEMS sensor interface circuits, fractional-N frequency synthesizers, high speed data converters and built-in-self-diagnostic circuits for high reliability and radiation aerospace applications. Dr. Bakkaloglu has been associate editor for IEEE Transactions on Circuits and Systems I and II, and an associate editor for IEEE Transactions on Microwave Theory and Techniques. He was the General Chair for 2015 RFIC Symposium. He is currently ON Semiconductor Professor of Electrical Engineering at Arizona State University.
RF Communications Consulting
Santa Clara, CA, USA
For leadership in polar modulation circuits and signals
Earl received his Bachelors, Masters, and Doctorate degrees at UC Berkeley, Stanford, and UC Davis respectively. His experience in RF circuits, signals, and systems goes back more than 40 years. Within this career he has founded two Silicon Valley startups, the first one, Digital RF Solutions, did modulated direct digital frequency synthesis in 1986 and merged with Proxim in 1991. The second start-up, Tropian, did switch-based RF transmitters from 1996 and was acquired by Panasonic 10 years later. He retired from Panasonic in 2008 as a Corporate Technology Fellow. Among other activities, he now also serves as a co-founder and the Chief Technology Officer of Eridan Communications, and is a full professor at TU Delft for sustainable wireless systems. He has 90 issued patents in the USA, with several more internationally. He is a double author with Cambridge University Press, first with Practical Digital Wireless Signals, and also with Dynamic Power Supply Transmitters. He is an IEEE MTT Distinguished Microwave Lecturer since 2013, now emeritus. He is appointed to the IEEE Green-ICT Initiative, and also serves on the standards committee within the IEEE 5G Initiative.
For contributions to CMOS integrated voltage-controlled oscillators
Pietro Andreani received the M.S.E.E. degree from the University of Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Sweden, in 1999. Between 2001 and 2007 he was chair professor at the Center for Physical Electronics, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund, Sweden. Since 2007, he has been associate professor at the dept. of Electrical and Information Technology (EIT), Lund University, working in analog/mixed-mode/RF IC design. He has also been the head of the VINNOVA Center for System Design on Silicon, hosted by EIT, between 2014 and 2016. He has been a TPC member of ISSCC (2007-2012), is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012, TPC chair in 2014) and RFIC, and Associate Editor of JSSC. He has been an IEEE SSCS Distinguished Lecturer since 2017. He has authored numerous papers on harmonic oscillators and phase noise, for which he has been elevated to IEEE Fellow in 2018.
For application of SRAM technology to low-power and high-performance computing
Dr. Jonathan Chang is a director leading memory IP development at TSMC. He is responsible for delivering SRAM compilers, custom SRAM IPs, efuse and OTP for low power, high speed applications for advance technology nodes. Before joining TSMC, Jonathan was a principal engineer at Intel responsible for 2nd/3rd level caches for Enterprise server processors. Jonathan received B.S. degree in electrical engineering from National Taiwan University, and M.S. and Ph.D. in electrical engineering from Stanford University. Jonathan is a senior member of IEEE, serves as TPC members for ISSCC, VLSI, guest editor of Journal of Solid State Circuits, and associate editor of IEEE Trans on VLSI. Jonathan has published 30+ technical papers in IEEE conferences or journals and held 25 patents in embedded memory design.
San Jose, CA
For contributions to transceivers for high-performance networking and high-density memories
Ken Chang (M 99, SM 14) received the B.S. degree in electrical engineering from National Taiwan University, Taiwan, in 1990, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, USA, in 1994 and 1999, respectively.
From 1999 to 2010, he was with Rambus. He led several projects including 5Gb/s/lane FlexIOTM interface for CELLTM processors, 16 Gb/s and 20 Gb/s low power memory interfaces exploring various signaling techniques. Since 2010, he has been with Xilinx. and currently serves as a Vice President. He has been leading the SerDes technology group, focusing on multi-standard SerDes IPs for FPGAs, covering 10Gb/s, 28Gb/s, and 56Gb/s line rates, all capable of long reach transmission. His research interests include high-speed mixed-signal CMOS circuit design, transmitter and receiver design, CDR, equalization, PLL/DLL design, circuit noise analysis, signal integrity analysis, and mixed signal design methodology.
He has authored and coauthored 50+ IEEE conference/journal publications and hold 40+ U.S. patents. He has served on technical program committees on VLSI circuit symposium, ISSCC, and CICC. He is the technical program co-chair of 2017 and chair of 2018 VLSI circuit symposium. He is the co-recipient of 2008 and 2014 CICC best regular papers. He is an IEEE fellow.
Hillsboro, OR, USA
For leadership in computer arithmetic datapath and security circuits
Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he leads research & development of energy-efficient hardware accelerators for encryption & security. He received the B. Tech. degree in electronics and communications engineering from the College of Engineering, Trivandrum, India, in 1993, and M.S. and Ph.D. degrees in electrical and computer engineering from The State University of New York at Buffalo, Buffalo, NY, USA, in 1996 and 1999, respectively. He joined Intel Corporation in 1999. He holds 43 issued patents, with another 61 patents pending and has published over 77 conference/journal papers. Dr. Mathew was a recipient of the 2012 ISSCC Distinguished Technical Paper Award, the 2012 ESSCIRC Best Paper Award, the Semiconductor Research Corporation Outstanding Industry Mentor Award. He was recognized as a “Prolific Contributor to ISSCC at 60th Anniversary Plenary at ISSCC 2013”. He has served on the technical program committees of the ARITH, ISLPED, DAC, and SOCC conferences.