IEEE Brokaw Award for Circuit Elegance
This award was established in 2018.
Integrated circuits have evolved into very complex systems, which can contain many millions of small elementary circuits constructed using a handful of transistors. Many of these circuits utilize known basic circuit techniques, often invented decades ago such as “bandgap” reference, AB amplifier bias stages, analog multipliers, various oscillators and even simple switches with bootstrap or charge canceling techniques. Each of these circuits exhibits an “elegancy” wherein several critical functions are combined in just a few components resulting from a highly creative process. One could compare these “elegancy” to a short yet beautiful poem, in the world of books or even movies. While the focus in IC design has shifted to complexity and functionality, the goal of the IEEE Brokaw Award for Circuit Elegance is to stimulate and celebrate the invention of elegant small circuits. "A few transistors doing a big job".
This Award was created to enhance appreciation and encourage innovation of simple, smart, and elegant circuit design. The Award will be presented in recognition of a unique, innovative, simple, smart, and elegant circuit design, which was created during the past decade and has demonstrated its viability.
This is an annual award and up to three designs may be recognized in a single year. Eligible candidates for this award must be SSCS members in good standing. Self-nominations are permitted.
Each design will receive a $10,000 cash prize and up to $5,000 for the designer to travel to attend ISSCC in the year of the award presentation. If more than one individual is responsible for the design, the cash prize will be split evenly among the designers.
There will be an open call for nominations via the communication channels of the Solid-State Circuits Society. Nominations must be received in the year prior to the year the award is presented. The deadline for submissions will be October 15th. Winner(s) will be notified by December 1st prior to the year the award is presented.
This award will be presented at ISSCC.
A platform called OpenWater is required to upload nomination packages. For detailed instructions on how to use the OpenWater platform, CLICK HERE.
The following materials must be uploaded as part of the nomination package:
1). A tutorial description of the elegant circuit. The submission does not need to describe an individual and complete IC. Rather, it may describe an important sub-function of a higher-level chip and may refer to a paper about the high-level chip. (PDF only, 25 MB Max)
2). An explanation of why the circuit is elegant according to the nominee (PDF only, 25 MB Max)
3). Proof of a working implementation, preferably lab test results. Thorough simulations demonstrating the function and resistance to environmental variables such as temperature and process variability will be considered (PDF only, 25 MB Max)
Incomplete nomination packages will not be accepted or considered.
Important Dates and Deadlines
Submission Deadline: October 15th
Winner Notification: December 1st
If you have any questions, contact Lauren Caruso, SSCS Administrator, firstname.lastname@example.org.