Terms through 31 December 2024
Presentation(s):
Electronic-photonic co-design; from imaging to optical phase control
Integrated electronic-photonic co-design can profoundly impact both fields resulting in advances in several areas such as energy efficient communication, computation, signal processing, imaging, and sensing. Examples of integrated electronic-photonic co-design may be categorized into two groups: (a) electronic assisted photonics, where integrated analog, RF, mm-wave, and THz circuits are employed to improve the performance of photonic systems, and (b) photonic assisted electronics, where photonic systems and devices are used to improve the performance of integrated RF, mm-wave, and THz systems. In this talk, examples of electronic-photonic co-design such as photonic assisted near-field imaging, photonic-mmWave deep networks, and low power laser stabilization and linewidth reduction will be presented.Integrated photonic deep networks for image classification
The typical hardware platform for neural networks operates based on clocked computation and consists of advanced parallel graphics processing units (GPU) and/or application specific integrated circuits (ASIC), which are reconfigurable, multi-purpose and robust. However, for such platforms the input data often needs to be converted to electrical domain, digitized, and stored. Furthermore, a clocked computation system typically has a high power consumption, suffers from a limited speed, and requires a large data storage device. To address the ever-increasing demand for more sophisticated and complex AI based systems, deeper neural networks with a large number of layers and neurons are required, which result in even higher power consumption and longer computation time. Photonic deep networks could address some of these challenges by utilizing the large bandwidth available around the optical carrier and low propagation loss of CMOS-compatible photonic devices and blocks. In this talk, a low-cost integrated highly-scalable photonic architecture for implementation of deep neural networks for image/video/signal classification is presented, where the input images are taken using an array of pixels and directly processed in the optical domain. The implemented system performs computation by propagation and, as such, is several orders-of-magnitude faster than state-of-the-art clocked based systems and operates at a significantly lower power consumption. This system, which is scalable to a network with a large number of layers, performs in-domain processing (i.e. processing in the optical domain) and as a result, opto-electronic conversion, analog-to-digital conversion, and requirement for a large memory module are eliminated.Presentation(s):
Current mode design techniques for low power transceivers
This talk will cover principles and application of current mode design techniques for ultra low power transceivers/signal generators. Current mode design techniques are becoming popular in recent times due to emergence of beamforming and AI/ML applications. In this talk, a few novel constructs for current mode designs shall be presented that are implemented using 14nm CMOS FinFET technology for qubit state controller (QSC) used for next generation quantum computing applications. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixerbased RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.Low power cryo-CMOS design for quantum computing applications
This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power currentmode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.Presentation(s):
Journey through the Memory Tunnel: SRAM, (e)DRAM, MRAM and RRAM Array Designs and Applications
Besides the classic PC and Server applications, the ever growing new AI and HPC applications are driving even more data processing, hence leads memory growth. SRAM and DRAM has been and will continue to be the main supplier of data processing memory. But there’re opportunities to invent new memories to close the performance-density gap in the memory hierarchies. This talk will go through the memory hierarchy and touch upon different memory types and their applications. It’ll also analyze emerging memories such as MRAM, RRAM and FeRAM and how it’d replace eFlash for embedded non-volatile memories.Presentation(s):
Digital equalization for Multilevel signaling in high-speed SerDes
Multilevel signaling has extended the lifeline of wireline signaling beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophisticated equalization that is more suitable for digital implementation. This presentation aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-based solutions. Starting from traditional analog architectures, this talk will walk through the evolution toward today’s DSP-based equalization and provide the background for tomorrow’s sequence decoding.Evolution of the Timing Recovery techniques in High-speed Links
Timing recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade, this evolution was motivated by technology scaling and scalability, where it gradually moved to a fully digital implementation from an analog PLL-based approach. However, the evolution in the last decade is motivated by the adoption of multilevel signaling. The emergence of MMSE as an alternative to 2X oversampled solutions is an example of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions, explain their motivation, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.Low-jitter flexible frequency generation for next-generation communication systems
The next-generation wireline and wireless systems promise wider bandwidth to enable a vast range of applications, including autonomous vehicles, virtual reality, and the internet of things. Such high data rates mandate precise clock generation to meet the timing budget. At the same time, flexibility to support multiple standards and scalability to meet higher integration density introduces additional dimensions to the clocking challenge. This talk will discuss recent circuit and architecture innovations to address these challenges. Starting from simple phase-locking concepts such as PLL, DLL and ILO, this talk will explain how the combination of these techniques is adopted in modern communication systems. It will also describe two example cases - i. A 28 GHz frequency synthesizer for 5G LO based beam forming, and ii. A flexible clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.Presentation(s):
An Overview on Interface Circuits and MPPT for Piezoelectric Energy Harvesting
Piezoelectric vibration-to-electricity conversion provides a feasible solution to self-sustainability due to its relatively high power density, wider voltage range, and the compatibility with IC technology. In the past decade, we have seen a booming of various interface circuits developed for piezoelectric energy harvesting. The drastic difference between the operating speed of integrated circuits and mechanical vibrations provides a perfect venue for performing nonlinear switching and control in the interface operation with low power, allowing orders of magnitude of improvement in power extracting ability.
This tutorial will cover a wide range of state-of-the-art interface designs and MPPT methods for piezoelectric energy harvesting, while emphasizing the circuit implementation considerations. Specifically, after describing the basic full-bridge and half-bridge rectifiers, the Synchronized-Switch-Harvesting (SSH) technique that is the foundation of all modern nonlinear interface circuits will be introduced. Two major categories, namely, the open-circuit and the short-circuit structures, are then discussed in details. After that, the common MPPT algorithms and implementations will be reviewed. This talk will also cover topics such as non-resonant operations and multiple-input piezoelectric energy harvesting systems.
Digitally-Enhanced Clock Generation and Distribution
Advancements in technology scaling have ushered in larger systems boasting enhanced functionality, increased operational speed, and expanded data bandwidth. However, these benefits come with more demanding clocking requirements, including extended distribution distances and heightened timing precision. Furthermore, technology scaling has rendered traditional analog design challenging. Wider PVT variations necessitate intensive calibration efforts, and increased integration levels call for resilience against external noise sources. Moreover, the fact that reference frequency and loop bandwidth do not scale at the same rate as technology leads to prohibitive costs for oversized loop filters. While pure analog implementations offer intuitive operation and elegant analysis, clocking circuits incorporating digital elements offer effective solutions to these challenges.
This presentation will cover how digital circuits can enhance clock generation and distribution through techniques like calibration and signal processing. Beginning with well-established methods that harness the mixed-signal nature of PLLs, such as delta-sigma modulation for the MDD in fractional-N PLLs, the presentation will shift toward digital-intensive architectures. It will focus on techniques that leverage digital implementations for error detection and enhance timing accuracy through either analog or digital correction. State-of-the-art designs featuring runtime calibration and power noise cancellation for clock generation and distribution will also be introduced. This talk will conclude with insights into future challenges and trends.
Presentation(s):
Designing an optimal hardware solution for deep neural network training
The size and complexity of recent deep learning models continue to increase exponentially, causing a serious amount of hardware overheads for training those models. Contrary to inference-only hardware, neural network training is very sensitive to computation errors; hence, training processors must support high-precision computation to avoid a large performance drop, severely limiting their processing efficiency. This talk will introduce a comprehensive design approach to arrive at an optimal training processor design. More specifically, the talk will discuss how we should make important design decisions for training processors in more depth, including i) hardware-friendly training algorithms, ii) optimal data formats, and iii) processor architecture for high precision and utilization.When circuits meet machine learning: circuit-based machine learning acceleration and machine learning-based circuit design
Pretrained deep learning models are strong against computation errors up to some extent, and this has sparked numerous ways of deep learning acceleration through circuit design techniques. Examples include time-domain computing, charge-domain computing, and feature extraction using analog circuits. However, non-ideal characteristics of transistors unavoidably lower their accuracy compared to their digital counterparts. Even if small, this drop could limit their usage in real-world applications. This talk discusses how we can close this performance gap at each design hierarchy level.
On the other hand, deep learning is now actively employed for hardware design automation. Large-scale digital systems have greatly benefited from these efforts, but automating low-level circuit design might be just around the corner. This talk introduces recent advances in circuit design automation with machine learning, from topology generation to size optimization and layout generation.
Presentation(s):
A Multi-Accelerator Appliance for Accelerating Inference of Hyperscale Transformer Models
Deep learning technology has made significant progress on various cognitive tasks, such as image classification, object detection, speech recognition, and natural language processing. However, the vast adaptation of deep learning also highlights its shortcomings, such as limited generalizability and lack of interpretability, also requiring manually-annotated training samples with sophisticated learning schemes. Witnessing the performance saturation of early models such as MLP, CNN, and RNN, one notable recent innovation in deep learning architecture is the transformer model introduced in 2017. It has two good properties towards artificial general intelligence over conventional models. First, the performance of transformer models continues to grow with their model sizes and training data. Second, transformers can be pre-trained with lots of unlabeled data through self-supervised learning and can be easily fine-tuned for each application.
In this talk, I will present a multi-FPGA acceleration appliance named DFX for accelerating hyperscale transformer-based AI models. Optimized for OpenAI’s GPT (Generative Pre-trained Transformer) models, it manages to execute an end-to-end inference with low latency and high throughput. DFX uses model parallelism and optimized dataflow that is model-and-hardware-aware for fast simultaneous workload execution among multiple devices. Its compute cores operate on custom instructions and support entire GPT operations including multi-head attentions, layer normalization, token embedding, and LM head. We implement the proposed hardware architecture on four Xilinx Alveo U280 FPGAs and utilize all of the channels of the high bandwidth memory (HBM) and the maximum number of compute resources for high hardware efficiency. Finally, DFX achieves 5.58× speedup and 3.99× energy efficiency over four NVIDIA V100 GPUs on the modern GPT-2 model. DFX is also 8.21× more cost-effective than the GPU appliance, suggesting that it can be a promising alternative in cloud datacenters.Processing-in-Memory for AI: From Circuits to Systems
Artificial intelligence (AI) and machine learning (ML) technology are revolutionizing many fields of study as well as a wide range of industry sectors such as information technology, mobile communication, automotive, and manufacturing. As more industries are adopting the technology, we are facing an ever-increasing demand for a new type of hardware that enables faster and more energy efficient processing for AI workloads.
Traditional compute-centric computers such as CPU and GPU, which fetch data from the memory devices to on-chip processing cores, have been improving their compute performances rapidly with the scaling of process technology. However, in the era of AI and ML, as most workloads involve simple but data-intensive processing between large-scale model parameters and activations, data transfer between the storage and compute device becomes the bottleneck of the system (i.e., von-Neumann bottleneck). Memory-centric computing takes an opposite approach to solve this data movement problem. Instead of fetching data from the storage to compute, data stays in the memory while the processing units are merged into it so that computations can be done in the same location without moving any data.
In this talk, I will briefly summarize the challenges of the latest AI accelerators focusing on the data movement issue mentioned above. Then, I will go through various processing-in-memory (PIM) architectures that can improve the performance and energy efficiency of the AI accelerators. I will also describe several notable circuit techniques on how we merge the logic into the memory and how we accelerate desired computations. Finally, I will propose a holistic approach to bridge the gap between the architectures and circuits and to make a practical and feasible PIM based solution for AI hardware.
Presentation(s):
Breaking the Phase-Noise Barrier with Multi-Core and Series-Resonance Harmonic Oscillators in BiCMOS Technology
The talk begins with a review of the fundamental and technological limiting factors to the spectral purity of integrated RF oscillators, and then proposes circuit solutions to break the phase noise barrier in silicon technology. Phase noise can be scaled by resorting to the multi-core approach, provided mismatches among multiple oscillators are carefully considered. As an example, a 16-core (voltage-controlled) oscillator demonstrates -130dBc/Hz at 1MHz offset from 20 GHz minimum phase. A more elegant and efficient approach is then introduced. Leveraging the series resonance of a tank, the remarkably lower resistance rises considerably the tank active power, thus enabling a remarkable improvement on the spectral purity. Two 10GHz BiCMOS VCOs exploiting the concept are proposed. The measured minimum phase noise is −138 dBc/Hz at 1-MHz offset with 600mW from 1.2-V supply. Experimental results demonstrate the lowest phase noise ever reported by fully integrated RF oscillators in a silicon technology.Presentation(s):
Automotive System Design
The automotive industry is in the midst of a significant transformation. “CASE: Connected, Autonomous, Shared & Service, Electric” has been advocated as a trend. Along with this trend, automotive E/E (Electrical/Electronic) architecture will evolve from the current distributed architecture to a domain architecture and then to the future zone architecture in the autonomous driving era. The lecture introduces the requirement of automotive system design for in-vehicle devices and their key technologies, including processors for the infotainment system and advanced vehicle control. The lecture also covers automotive functional safety, security, and maintenance & upgrades with OTA(Over the air).Presentation(s):
Challenges in Battery Monitoring Systems for Electrical Vehicles
Electrical vehicles will become the standard in private transport the coming decade. Since the battery is still the main component that will determine cost and driving range, a good battery control is the main component in an eV system. A battery management system consists of 2 components : a current measurement system and a voltage monitoring system. Both have their own specific problems. We will first discuss the different techniques to measure current : using a shunt, a Rogowski coil or using a magnetic sensor. Next the voltage measurement chain will be tackled including techniques for dealing with the high voltages of a battery pack.Design of Fully Integrated Charge Pumps
In this lecture we will discuss the basics of charge pump design. Starting with the fundamental observation that half of the energy is lost when charging a capacitor, the principle of quasi-static charging is explained. From these charge balancing laws, the basic model of a charge pump can be derived together with the slow switching limit and fast switching limit. This on its turn leads to the PFM control loop to regulate the output power. All this is illustrated with several examples like a Dickson Charge Pump, a series-parallel converter, the Fibonacci converter, … and more advanced techniques like multi-phase are touched. In the second part, a real life design plan is shown where starting from the specifications a topology is developed and simulated.Design of High Performance Readout Chains for MEMS Barometric Pressure Sensors
Barometric pressure sensor are indispensable features in wearable consumer devices. Modern designs can sense absolute height difference of less than 8.5cm (1Pa), improving indoor navigation significantly and enabling new applications such as activity tracking and crash detection. In this talk, we will take a deep dive into the design challenges of readout chains for capacitive pressure sensors. The main driving requirements are noise and power. To reach the demanding targets for wearable devices, heavy duty cycling and advanced analog front-end design is needed. But these are not the only challenges. Since they must be exposed to the atmosphere, pressure sensors in smartphones are often located in their outer cases, and have long connections to the main PCB. This leads to high demands on their PSRR and RF immunity. Both topics will be discussed, as well as several methods to improve the robustness of pressure sensor readout chains.High Performance, Low Power 3D Magnetic Hall Sensor design and challenges
Magnetic sensors are everywhere, from the accurate current measurement applications over wheel speed sensors to magnetic switches that measure the angle of your laptop case. In the field of magnetic sensors, the Hall effect sensor plays an important role for its high linearity and since it is fully integrated in almost any semiconductor technology. In this lecture we will cover the basics of a hall plate sensor, starting with the 1D hall plate and extending this to integrated 3D sensors. One of the drawbacks of a hall plate is its high offset. Techniques for reducing this non-ideality like quadrature layout and spinning will be elaborated. A full analog readout chain will then be further discussed with an emphasis on the instrumentation amplifier including best design practices and simulation techniques.Presentation(s):
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators
In this seminar, we will present a thorough review of the recent digital low-dropout voltage regulators (DLDOs). We have reviewed them in five aspects: control laws, triggering methods, power-FET circuit design, digital-analog hybridization, and single vs. distributed architectures. We then surveyed and benchmarked over 50 DLDOs published in the last decade. In addition, we have offered a new figure of merit (FoM) to address the shortcomings of the previously proposed FoMs. The benchmark provides insights into which techniques contribute to better dynamic load regulation performance. The survey and benchmark results are uploaded to a public repository.SRAM-based In-Memory Computing Hardware: Analog vs Digital and Macros to Microprocessors
In the last decade, SRAM-based in-memory computing (IMC) hardware has received significant research attention for its massive energy efficiency and performance boost. In this seminar, first, we will introduce two very recent macro prototypes which achieve state-of-the-art performance and energy efficiency yet leverage very different computing mechanisms. Specifically, one adopted analog-mixed-signal (AMC) computing mechanisms (capacitive coupling and charge sharing), whereas the other adopted a fully digital approach. After this macro-level introduction, we will present recent microprocessor prototypes that employ IMC-based accelerators, which can perform on-chip inferences at very high energy efficiency and low latency.Presentation(s):
FPGA-Chiplet Architectures and Circuits for 2.5D/3D 6G Intelligent Radios
The number of connected devices is expected to reach 500 billion by 2030, which is 59-times larger than the expected world population. Objects will become the dominant users of next-generation communications and sensing at untethered, wireline-like broadband performance, bandwidths, and throughputs. This sub-terahertz 6G communication and sensing will integrate security and intelligence. It will enable a 10x to 100x increase in peak data rates. FPGAs are well positioned to enable intelligent radios for 6G when coupled with high-performance chiplets incorporating RF circuits, data converters, and digital baseband circuits incorporating machine learning and security. This talk presents use of 2.5D and 3D heterogeneous integration of FPGAs with chiplets, leveraging Intel’s EMIB/Foveros technologies with focus on one emerging application driver: FPGA-based 6G sub-THz intelligent wireless systems. Nano-, micro-, and macro-3D heterogeneous integration is summarized, and previous research in 2.5D chiplet integration with FPGAs is leveraged to forge a path towards new 3D-FPGA based 6G platforms. Challenges in antenna, packaging, power delivery, system architecture design, thermals, and integrated design methodologies/tools are briefly outlined. Opportunities to standardize die-to-die interfaces for modular integration of internal and external circuit IPs are also discussed.Laying the Foundation for Intelligently Adaptive Radios
System adaptivity has been studied since the mid-60s and recently there has been a surge in interest in self-adaptive systems, especially in the software engineering community, with its main application is cybernetics. This talk introduces the concept of a self-adaptive system as it is extended to wireless communication, where channel characteristics are exploited to intelligently modify operation of the physical layer of the radio to optimize energy consumption and connectivity. The architectural and circuit foundations required to realize a wide-band “learning-based” transceiver architecture are detailed in the design and implementation of configurable PHY subsystems that can be dynamically programmed to realize intelligent radios. Current advancements in the application of AI/ML to wireless systems and how these may be leveraged at the PHY level are briefly discussed followed by an overview of future research required to build intelligently adaptive radio systems.Presentation(s):
3D millimeter-wave imaging and sensing with Si-based phased arrays, edge computing, and AI
The use of millimeter-wave frequencies for 5G networks has been a primary contributor for transitioning Si-based phased array technology from R&D to real-world deployments. While the commercial use of millimeter-wave sensing so far has been dominated by low-cost, compact MIMO radars for automotive and industrial applications, the on-going wide deployment and advancement of Si-based phased arrays opens a new horizon of opportunities for sensing and event recognition. This talk will first cover the fundamentals and KPIs of 3D radar systems using phased arrays including associated key circuit design and packaging design techniques. Examples of such 3D radar systems at 28-GHz, 60-GHz and 94-GHz will be provided. Next, the presentation will describe how the full potential of such systems can be realized through synergistic co-design with algorithms and edge computing assets. Key examples of emerging applications based on these vertically integrated antennas-to-software/AI systems will be provided including multi-spectral imaging, 5G mmWave joint sensing and communications, and AI-based recognition of human gestures and concealed objects.Packaging and module integration as a catalyst for innovation in Si-based millimeter-wave systems
Over the last two decades, advancements on Si-based electronics enabled the development of wireless systems operating at millimeter-wave frequencies. Along the way, advanced package designs and component integration technologies were crucial in enabling those systems to reach their full potential and, more importantly, achieve commercial impact. As we enter the maturing stage of 5G and start seeing the dawn of 6G on the horizon, mmWave systems are expected to play a growing role in high-throughput wireless communications and a large variety of sensing applications. This talk will first review key milestones in the history of mmWave module development with focus on phased arrays. The lessons learned from this journey will be described, with emphasis on antenna-in-package design and IC-package co-design. Then, emerging mmWave systems and applications will be described including the software-defined phased array, a multi-spectral imaging platform, and AI-based feature extraction from 3D radar. The presentation will conclude by outlining the next set of challenges that IC, package, and module integration technologies need to address to enable the realization of those system concepts and as compact “Antennas-to-AI” heterogeneous modules.Presentation(s):
CMOS Power Amplifiers and Transmitters: The Evolution from 'Digital-Friendly' RF to 'Digital' RF
Abstract not yet available.Digitally Friendly Transmitters for Next Generation Communications
Abstract not yet available.Mixed-Mode Transceivers in CMOS
Abstract not yet available.Presentation(s):
Machine Learning Hardware Design for Efficiency, Flexibility and Scalability
Machine learning (ML) is the driving application of the next-generation computational hardware. How to design ML hardware to achieve a high performance, efficiency, and flexibility to support fast growing ML workloads is a key challenge. Besides dataflow-optimized systolic arrays and single instruction, multiple data (SIMD) engines, efficient ML accelerators have been designed to take advantage of static and dynamic data sparsity. To accommodate the fast-evolving ML workloads, matrix engines can be integrated with an FPGA to provide the efficiency of kernel computation and the flexibility of control. To support the increasing ML model complexity, modular chiplets can be tiled on a 2.5D interposer and stacked in a 3D package. We envision that a combination of these techniques will be required to address the needs of future ML applications.The Challenges and Opportunities in the Path Towards Chipletization
The modular partition into chiplets and the integration of chiplets in 2.5D or 3D forms offer a promising path towards constructing large-scale systems to deliver a performance comparable to single-chip integration, but without the high cost, risks and effort associated with monolithic integration. Industry has shown us what are possible with chipletization. However, for the technology to truly take off, we need three key elements to be in place: chiplets equipped with a standard interface, advanced bumping and packaging technology, and design automation. I will share our journey in conducting research on chipletization and the development of chiplets, all equipped with a standard-conforming, sub-pJ/b, synthesizable I/O interface. Through collaborations, we demonstrated multi-chip packages by tiling homogeneous chiplets and integrating heterogeneous multi-functional chiplets to efficiently scale up systems and improve their performance and versatility. Our lessons taught us that the success of chipletization must rely on an ecosystem that lowers the entry barriers, and the best practice in chipletization is to employ cross-domain endeavors that span system design, IC design, packaging, and assembly.Terms through 31 December 2025
Presentation(s):
Adaptive Processor Designs
System-on-chip (SoC) processors across a wide range of market segments, including Internet of Things (IoT), mobile, laptop, automotive, and datacenter, experience dynamic device, circuit, and system parameter variations during the operational lifetime. These dynamic parameter variations, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations, degrade processor performance, energy efficiency, yield, and reliability. This lecture introduces the primary variation sources and the negative impact of these variations across voltage and clock frequency operating conditions. Then, this lecture presents adaptive processor designs to mitigate the adverse effects from dynamic parameter variations while highlighting the key trade-offs and considerations for product deployment.Presentation(s):
High-Performance PLLs: Evolution, Challenges, and Future Directions
High-performance phase-locked loop (PLL) is one of the key techniques for both communication and radar systems, which makes it to be the cutting-edge topic in the field of integrated circuit and system design. It involves various research directions such as mixed-signal circuit design, digital algorithms, and system-level architecture. This lecture will discuss the high-performance PLL circuit and architecture evolution, review the latest research progress and discuss the future development trends of high-performance PLLs, with particular emphasis on ultra-low jitter PLLs toward 10-fs.rms and FMCW PLLs with ultra-fast and linearized chirp in CMOS technology.Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design
Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. This lecture will introduce the current and future trends in the emerging joint radar-communication CMOS transceiver from system architecture to circuit design.Presentation(s):
High-Speed DACs for 100+ Gb/s Wireline Links
Digital-to-analog converters (DACs) operating above 50GS/s are critical components of modern transmitters for wireline applications. These circuits permit data modulation and equalization to be moved from the analog domain (as was common in links operating below 50Gb/s) to the digital domain, thereby enabling today’s serial links operating at 100-200Gb/s. This lecture explores DAC design for wireline applications. Driver and multiplexer design techniques will be introduced, including those used for current-mode (CML) and voltage-mode (SST) drivers found in state-of-the-art serial links. As systems explore the use of more sophisticated modulation formats such as higher-order time domain pulse amplitude modulation (e.g., PAM6 or PAM8) or frequency domain modulation (e.g., OFDM), higher linearity DACs will be required than those employed in existing PAM4 systems. Techniques for adaptive calibration of DAC static linearity will be discussed. Designs of two different 8b DACs operating at 56 and 72GS/s in 7nm and 4nm FinFET technologies will be described as case studies.Presentation(s):
AI accelerators and the chiplet paradigm
The growth in the application of machine learning and artificial intelligence technology to problems across virtually all spheres of endeavor has been and is expected to remain extraordinary. Hardware acceleration for machine learning tasks is a critical vector that has enabled this exceptionally rapid growth. Further accelerator advances are necessary to drive everything from improved efficiency for inference, to support ever-growing network sizes to improvements in support for network training, to enabling broadening of ML deployments across platforms with a wide range of power and performance envelopes. The emerging chiplet paradigm will drive not only the scaling of compute density in AI solutions, but also promises to enable a proliferation of customized AI solutions for a range of workloads. In this presentation, we will describe example AI accelerator designs in the context of a solution framework, how communication advances are linked AI accelerator advancement, and will discuss approaches to accelerate the emergence of a chiplet ecosystem, including how this emergence might drive new accelerator implementation opportunities.Cryogenic CMOS for future scaled quantum computing systems
Quantum computing represents a new paradigm that has the potential to transform problems that are computationally intractable today into solvable problems in the future. Significant advances in the last decade have lent support to the idea that quantum computers can be implemented, and further that the goal of demonstrating true performance advantages over traditional computing techniques on one or more problems may be achieved in the not so distant future. Delivering on this promise is expected to require quantum error correction solutions, in turn demanding large qubit counts that pose significant challenges for quantum computer implementations, especially in the area of qubit interface electronics. An active area of research to address this challenge is the use of integrated cryogenic CMOS designs. In this presentation, we will present a superconducting qubit-based quantum computing system framework, opportunities for cryogenic CMOS introduction into future systems, example cryogenic CMOS implementations and results, and next challenges that must be met to enable cryogenic CMOS adoption.Presentation(s):
Acceleration of Encryption Algorithms, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic Encryption (FHE)
This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, CRISTALS-Kyber/Dilithium, isogeny based encryption argorithms, and fully homomorphic encryption algorithm.Basics of Asynchronous circuits design
This lecture will overlook basics and variety of asynchronous controlling, from the view point of advantages for low-voltage & variation rich conditions. This lecture takes two extreme example of complete completion detection type asynchronous designs as examples and demonstrate details of operation and performance. In addition, this talk will cover recent trial on design flow of random logic by the self-synchronous circuits.Low-voltage design with autonomous control by gate-level hand-shaking
This lecture will cover basics of asynchronous control including complete completion detection type control, and demonstrate the autonomous gate-level power gating to reduce energy consumption at the energy minimum operating point with asynchronous FPGA as the example. This lecture will also cover low-voltage operations, operation tolerance with power bounce, as well as aging. In addition, this talk will cover recent trial on design flow of random logic by the self-synchronous circuits.Presentation(s):
Energy-Efficient Sensor Interface
In the IoT era, a miniaturized sensor system serves as a key leaf node by collecting environment signals and bio-potentials. However, due to the small form factor and limited battery capacity, the energy efficiency of analog and mixed-signal circuits is a critical concern for the long-term operation of the sensor system. Especially, it poses a crucial challenge for the sensor interface circuits whose power consumption needs to be minimized while maintaining acquired signal accuracy and bandwidth. This short course discusses various sensor interface designs with improved noise and power efficiency.Fully integrated DC-DC Conversion
Power management integrated circuits are essential building blocks of consumer electronics for the Internet of Things. Among various architectures, fully integrated power management circuits are promising candidates to provide small form factors and meet the high power density demand of modern computing platforms. However, several characteristics of on-chip passive components limit the performance of the fully integrated DC-DC converters, such as small inductance and Q-factor of the on-chip inductors and large parasitic bottom capacitance or low density of the on-chip capacitors. This short course will introduce the fundamentals of on-chip DC-DC converter designs as well as the latest designs with improved performance.Low Power Frequency Generation
Miniaturization and Interactive communication have been the two main topics dominating recent research on the internet-of-things. The high demand for continuous monitoring of environmental and bio-medical information has accelerated sensor technologies as well as circuit innovations. Simultaneously, the advances in communication methods and the widespread use of cellular and local data links enabled the networking of miniaturized sensor systems. In such systems, the reduction of sleep power is critical to make them sustainable with limited battery capacity or harvested energy. It makes the ultra-low-power wake-up timer a critical building block that must be designed with a stringent power budget. At the same time, precise frequency accuracy is also essential to maintaining synchronization for data communication. This short course will present fundamentals and recent innovations in ultra-low-power frequency reference circuits for miniaturized IoT systems. Two commonly adopted architectures, on-chip RC oscillators, and crystal oscillators, are introduced and discussed in terms of power consumption, noise, temperature sensitivity, line sensitivity, and calibration methods. Finally, a summary of the state-of-the-art designs and related challenges will be introduced.Presentation(s):
Current-Shared Cluster of Multiple Integrated Voltage Regulators (IVRs)
Ganging multiple integrated voltage regulators (IVRs) is crucial for delivering sufficient power in system-on-chip (SoC) applications, particularly those with heavy workloads. However, the utilization of ganged voltage regulators in a shared power-grid is often faces challenges due to supply-current imbalances among the regulators, resulting in larger voltage ripples and thermal hotspots that compromise reliability. The issue is further intensified in inductive-switching IVRs by their tightly spaced on-chip inductors and high switching frequencies, which exacerbate current imbalances.
In this talk, we will explore the state-of-the-art current-sharing techniques for multi-phase IVRs and distributed digital LDOs. We will closely investigate two chip design cases: a 6-phase IVR using bond-wire inductors and a 4-phase IVR with on-chip spiral inductors, focusing on flying-capacitor-based topological solutions for inter-inductor current balancing. Additionally, this talk will include cost-effective solutions to enhance current-sharing accuracy in distributed digital LDO systems without the need for complicated global control mechanisms.
Display Driver ICs – From Basics to Recent Design Challenges
Display driver ICs (DDIs), tasked with digital-to-analog conversion (DAC) and signal drive into pixels, drastically impact image quality in OLED and LED displays. The growing demand for higher visual realism, even in mobile displays, necessitates integrating more source channels into each DDI. Given that the DAC occupies a significant portion of the die area, boosting area efficiency becomes imperative in DDI design to accommodate more channels on a single chip without sacrificing color depth. Moreover, the trend towards high-frame-rate displays (beyond 60Hz) aims to enhance user experience, but faces limitations due to the output buffer’s slew rate in DDIs. Additionally, the emergence of VR/AR micro-displays is introducing new design challenges for CMOS driver and pixel circuits.
This talk will provide a comprehensive investigation of DDI designs, covering foundational principles, technical challenges, and the latest innovations. We will start with an overview of DDIs, assessing their performance across key metrics such as data resolution, die area per channel, linearity, inter-channel deviation, conversion speed, drivability, and power consumption. This talk will then pivot to strategies for balancing some of the performance metrics in DDI design and showcase advanced architectural solutions. It will also cover the progress and hurdles in micro-display drivers, particularly for OLED-on-Silicon and μLED-on-Silicon technologies. In addition, DDIs embedding pixel-current sensing capabilities will be introduced, examining their potential for preemptively addressing burn-in issues.
Exploring Ways to Minimize Dropout Voltage for Energy-Efficient LDO Regulators
Low-dropout (LDO) regulators are ideal off- and on-chip solutions for powering noise-sensitive loads due to their ripple-less output. LDOs also have many benefits over switch-mode dc-dc converters, such as rapid transient response, excellent power supply rejection (PSR), and compact footprint. Unfortunately, they suffer from an inescapable disadvantage: poor power efficiency; this is primarily caused by a considerable dropout voltage (VDO). Reducing VDO to improve efficiency often leads to a significant drop in LDO’s regulation performance. Because of this, most LDOs are designed with a large VDO, making them perceived as energy-consuming components of power management systems.
This talk will delve into effective ways to extremely minimize the dropout voltage without compromising performance, aiming for energy-efficient LDO regulators. We will begin with a thorough investigation of operational principles, analyses, and strategies, exploring trade-offs among key performance metrics. Next, several promising approaches to realizing energy-efficient LDO regulators will be investigated, including traditional digital LDOs, a dual-rail analog/digital-hybrid LDO, a triode-region LDO, and a voltage/current-hybrid (VIH) LDO. Finally, the technical merits and flaws of each high-efficiency LDO topology will be investigated by comparing them. In this talk, I will also share my insights from my experience developing the VIH LDO regulator that achieves 98.6% efficiency and a -75dB PSR at 30kHz.
Presentation(s):
All-In-One Data Decoders Using GRAND
In 1948, Shannon stated that the best error correction performance comes at longer code lengths. In 1978, Berlekamp, McEliece, and Tilborg established that optimally accurate decoding of linear codes is NP-complete in code length, so there is no optimally accurate universal decoder at long code lengths. Forward error-correction decoding has traditionally been a code-specific endeavor. Since the design of conventional decoders is tightly coupled to the code structure, one needs a distinct implementation for each code. The standard co-design paradigm either leads to significantly increased hardware complexity and silicon area to decode various codes or restrictive code standardization to limit hardware footprint. An innovative recent alternative is noise-centric guessing random additive noise decoding (GRAND). This approach uses modern developments in the analysis of guesswork to create a universal algorithm where the effect of noise is guessed according to statistical knowledge of the noise behavior or through phenomenological observation. Because of the universal nature of GRAND, it allows efficient decoding of a variety of different codes and rates in a single hardware instantiation. The exploration of the use of different codes, including heretofore undecodable ones, e.g., Random Linear Codes (RLCs), is an interesting facet of GRAND. This talk will introduce universal hard-detection and soft-detection decoders using GRAND, which enables low-latency, energy-efficient, secure wireless communications in a manner that is future-proof since it will accommodate any type of code.
This work is joint with Muriel Medard (MIT) and Ken Duffy (Northeastern University).
Cyber-Secure Biological Systems (CSBS)
This talk will introduce Cyber-Secure Biological Systems, leveraging living sensors constructed from engineered biological entities seamlessly integrated with solid-state circuits. This unique synergy harnesses the advantages of biology while incorporating the reliability and communication infrastructure of electronics, offering a unique solution to societal challenges in healthcare and environmental monitoring. In this talk, examples of Cyber-Secure Biological Systems, such as miniaturized ingestible bioelectronic capsules for gastrointestinal tract monitoring and hybrid microfluidic-bioelectronic systems for environmental monitoring, will be presented.Physical-Layer Security for Latency- and Energy-Constrained Integrated Systems
The boom of connected IoT nodes and ubiquity of wireless communications are projected to increase wireless data traffic by several orders of magnitude in the near future. While these future scalable networks support increasing numbers of wireless devices utilizing the EM spectrum, ensuring the security of wireless communications and sensing is also a critical requirement under tight resource constraints. The physical layer has increasingly become the target of attacks by exploiting hardware weaknesses, e.g., side-channel attacks, and signal properties, e.g., time, frequency, and modulation characteristics. This talk introduces common security vulnerabilities within wireless systems such as jamming, eavesdropping, counterfeiting, and spoofing, followed by physical-layer countermeasures, while assessing the trade-offs between performance and security. It examines recent research directions, e.g., secure spatio-temporal modulated arrays, temporal swapping of decomposed constellations, RF fingerprinting, and bit-level frequency hopping, and finally discusses research opportunities looking forward.Presentation(s):
Hardware Security and Safety of IC Chips and Systems
IC chips are key enablers to a smartly networked society and need to be more compliant to security and safety. For example, semiconductor solutions for autonomous vehicles must meet stringent regulations and requirements. While designers develop circuits and systems to meet the performance and functionality of such products, countermeasures are proactively implemented in silicon to protect against harmful disturbances and even intentional adversarial attacks. This talk will start with electromagnetic compatibility (EMC) techniques applied to IC chips for safety to motivate EMC-aware design, analysis, and implementation. It will discuss IC design challenges to achieve the higher levels of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, corroborated with silicon demonstrating analog techniques to protect digital functionality. The EMC and HWS disciplines derived from electromagnetic principles are key to establishing IC design principles for security and safety.IC Chip and Packaging Interactions for Performance Improvements and Security Protections
Interactions of IC chips and packaging structures differentiate the electronic performance among traditional 2D chips and advanced 2.5D and 3D technologies. This presentation starts with their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements as well as full-chip and system level noise simulation. Additionally, the backside of an integrated circuit (IC) chip, more precisely, the backside surface of its Silicon substrate, provides open areas for circuit performance improvements and adversarial security attacks, that are potentially contradictory or traded off in design for performance and security. The talk also explores the security threats over the Si-substrate backside from both passive and active side-channel attack viewpoints and then discusses countermeasure principles.RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance of IC Chips and Systems
Noise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by full-chip and system level simulation. Power and substrate integrity simulation uses chip-package-system board combined models and verifies noise coupling in mixed RF and analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wireless performance through quantitative metrics (e.g. communication throughput and minimum receivable power) among various wireless systems of such as 4G, 5G and GPS. In addition, post-silicon techniques at packaging and assembly stages are potential options to mitigate RF noise coupling problems. The presentation will also include experimental test cases of wireless power transfer modules and unmanned aerial vehicles (drones).Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips
Semiconductor products are potentially compromised for theft, falsification or invalidation by adversarial attempts and even due to unexpected disturbances. This talk provides an overview of physical security threats among semiconductors, and then discusses a broad range of countermeasure techniques. Secure packing exploits vertical structures using post wafer process technologies such as through Si vias, Si backside membranes and Si interposers for proactive prevention from destructive or nondestructive intrusions. Tamper resistance is achieved at the IC level with analog techniques to protect digital functionality. Supply chain security uses hardware Trojan free design verification as well as authentication strategies. Silicon examples will be demonstrated.Presentation(s):
Efficient High Resolution Incremental ADCs
High-resolution, high-efficiency converters are dominated by noise-shaping and oversampling architectures. However, in applications where true Nyquist-rate conversion is required, such as single-shot conversion, multiplexing, or time-interleaving, neither oversampling nor noise-shaping can be used. This is due to the very concepts that allow them to combine efficiency with performance, introduce memory into the system, and thus prevent sample-to-sample operation. This talk presents approaches to get around this, i.e. to combine Nyquist rate conversion with high power efficiency through innovative architecture and circuit design with a focus on incremental delta-sigma ADCs.Implantable Integrated Circuits and Systems for Neurostimulation and Neuromodulation
Implantable medical devices (IMD) are widely used today to restore function to people with disabilities such as deafness, blindness, heart failure, incontinence, neurological disorders, and many others. Such implantable systems become increasingly challenging when a large number of sensing or stimulating sites need to be realized - space and power budget, safety issues, high bidirectional data rates, as well as the large number of electrical interfaces make the electronic circuit design a complex task of research and development. This talk will highlight some of the recent progress towards the realization of high channel count implantable neural interfaces, covering applications and system examples of neural modulators with high efficiency frontends.Presentation(s):
Continuous-Time Pipelined Analog-to-Digital Converters - Where Filtering Meets Analog-to-Digital Conversion
If someone told you that the power, noise, distortion, and area of a mixed-signal block could be reduced all at the same time, you'd probably think that this was a lie. It turns out that it is indeed possible sometimes - and this talk will present an example called the continuous-time pipeline (CTP) ADC. The CTP is an emerging technique that combines filtering with analog-to-digital conversion. Like a continuous-time delta-sigma modulator (CTDSM), a CTP has a "nice" input impedance that is easy to drive and has inherent anti-aliasing. However, unlike a CTDSM, a CTP does not require a high-speed feedback loop to be closed. As a result, it can achieve significantly higher bandwidth (like a Nyquist ADC). After discussing the operating principles behind the CTP, we describe the fundamental benefits of the CTP over a conventional signal chain that incorporates an anti-alias filter and a Nyquist-rate converter. We will then show design details and measurement results from a 12-bit ENOB, 100MHz 800MS/s CTP designed in a 65nm CMOS process.Design Challenges in Precision Continuous-Time Delta Sigma Data Conversion
Energy-efficient, high-resolution continuous-time delta-sigma modulators need to overcome several issues that are typically neglected in the design of data converters that target more modest in-band noise spectral densities. Examples of such problems include flicker noise, interconnect resistance and DAC inter-symbol-interference. This talk aims to provide some insight into these issues and describe techniques that can be used to address the formidable challenge of designing such converters. To place things in perspective, the techniques will be discussed in the context of single- and multi-bit CTDSMs that achieve about 105dB SNDR in a 250kHz bandwidth designed in a 180nm CMOS process.Presentation(s):
Recent Circuit Advances for Resilience to Side-Channel Attacks
Computationally secure cryptographic algorithms, when implemented on physical hardware, leak correlated physical signatures (e.g. power supply current, electromagnetic radiation, acoustic, thermal) which could be utilized to break the crypto engine. Physical-layer countermeasures, guided by understanding of the physical leakage, including circuit-level and layout-level countermeasures promise strong resilience by reducing the physical leakage at the source of the leakage itself. The past decade has seen significant advancements in circuit-level countermeasures, advancing resilience to side-channel attacks. In this talk, we will cover the fundamentals of the leakages and how each countermeasure increases resilience, by diving into the working mechanism of each and comparing the pros and cons of these techniques. The talk concludes by highlighting the open problems and future needs of this field.Secure and Efficient Internet of Bodies using Electro-Quasistatic Human Body Communication
Radiative communication using electromagnetic (EM) fields is the state-of-the-art for connecting wearable and implantable devices enabling prime applications in the fields of connected healthcare, electroceuticals, neuroscience, augmented and virtual reality (AR/VR) and human-computer interaction (HCI), forming a subset of the Internet of Things called the Internet of body (IoB). However, owing to such radiative nature of the traditional wireless communication, EM signals propagate in all directions, inadvertently allowing an eavesdropper to intercept the information. Moreover, since only a fraction of the energy is picked up by the intended device, and the need for high carrier frequency compared to information content, wireless communication tends to suffer from poor energy-efficiency (>nJ/bit). Noting that all IoB devices share a common medium, i.e. the human body, utilizing the conductivity of the human the body allows low-loss transmission, termed as human body communication (HBC) and improves energy-efficiency. Conventional HBC implementations still suffer from significant radiation compromising physical security and efficiency. Our recent work has developed Electro-Quasistatic Human Body Communication (EQS-HBC), a method for localizing signals within the body using low-frequency transmission, thereby making it extremely difficult for a nearby eavesdropper to intercept critical private data, thus producing a covert communication channel, i.e., the human body as a ‘wire’ along with reducing interference.
In this talk, I will explore the fundamentals of radio communication around the human body to lead to the evolution of EQS-HBC and show recent advancements in the field which has a strong promise to become the future of Body Area Network (BAN). I will show the theoretical development of the first Bio-Physical Model of EQS-HBC and how it was leveraged to develop the world’s lowest-energy (<10pJ/b) and world’s first sub-uW Physically and Mathematically Secure IoB Communication SoC, with >100x improvement in energy-efficiency over Bluetooth. Finally, I will highlight the possibilities and applications in the fields of HCI, Medical Device Communication, and Neuroscience including a few videos demonstrations. We will also highlight how such low-power communication in combination with in-sensor intelligence is paving the way forward for Secure and Efficient IoB Sensor Nodes.
Presentation(s):
The Historical Development of Data Converters – ADCs that last from 1954 to 2024
Data Converters are one of the key building blocks and the performance bottleneck in the various applications of integrated circuits in our daily lives. The development of data converters is the fundamental driving force behind the modern technology of smart mobile devices based on sensors, communication, and artificial intelligence. However, Data Converters, e.g. SAR ADCs, already have a long history; they served as the key to improving human electronics technology even in the long past, modern, and the foreseeable future. This talk will present the historical development of data converters and review the key data converter development trends in the current era and what we can do.Weightings in Incremental ADCs – How the weights can break and make the Incremental ADCs
Incremental delta-sigma analog-to-digital converters (IADC) are widely used in modern high-fidelity audio, sensors, and IoT low-power applications. Over the past years, the techniques to implement high-resolution IADCs have been significantly improved, for example, in handling the weighting problems inside the IADCs to overcome thermal noise and DAC mismatch issues. This talk offers a comprehensive review of the considerations of weightings in IADCs. The influence of weightings on thermal noise and DAC mismatches are analyzed, and the use of weighting in algorithms is described specifically. The advanced architectures to take advantage of the weightings based on recent academic achievements are presented respectively, with design examples to illustrate the successful practical implementations.Presentation(s):
Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
The compute demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed; the increasingly complex algorithms for higher quality of results; and the demands for energy efficiency and real-time performance. In this talk, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption while delivering real-time and robust performance for applications including deep neural networks, data analytics with sparse tensor algebra, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduce the cost of analog-to-digital converters for processing-in-memory accelerators. Throughout the talk, we will highlight important design principles, methodologies, and tools that can facilitate an effective design process.Efficient Computing for Autonomy and Navigation
A broad range of next-generation applications will be enabled by low-energy autonomous vehicles including insect-size flapping wing robots that can help with search and rescue, chip-size satellites that can explore nearby stars, and blimps that can stay in the air for years to provide communication services in remote locations. Autonomy capabilities for these vehicles will be unlocked by building their computers from the ground up, and by co-designing the algorithms and hardware for autonomy and navigation. In this talk, I will present various methods, algorithms, and computing hardware that deliver significant improvements in energy consumption and processing speed for tasks such as visual-inertial navigation, depth estimation, motion planning, mutual-information-based exploration, and deep neural networks for robot perception. We will also discuss the importance of efficient computing to reduce carbon footprint for sustainable large-scale deployment of autonomous vehicles.
Much of the work presented in this talk was developed in the Low-Energy Autonomy and Navigation (LEAN) interdisciplinary group at MIT (http://lean.mit.edu), which is co-directed by Vivienne Sze and Sertac Karaman.
Presentation(s):
Body Area Network – Connecting and powering things together around the body
Body Area Network (BAN) is an attractive means for continuous and pervasive health monitoring, providing connectivity and power to the sensors around the human body. Yet its unique and harsh environment gives circuit designers many challenges. As the human body absorbs the majority of RF energy around the GHz band, existing RF radio may not be ideal for communications between and on-body sensors, and so is the RF wireless power transfer. When it comes to energy harvesting, often the harvesting location is not aligned with the sensor location (a.k.a. location mismatch).
To solve the issues, this talk presents the Body Coupled Communication (BCC)-based BAN. BCC BAN utilizes the human body itself as a communication medium, which has orders of magnitude less pathloss when compared to RF in the BAN environment. We will begin with channel characteristics followed by design considerations and transceiver implementation examples. We will then look into what circuit designers should consider in such non-conventional environments. Low energy circuit techniques to overcome their limitations will also be addressed. Lastly, we will discuss the various system aspects of the BAN, including powering up the wearables using the wearable BAN.
Low-power, Low-noise Sensor Interface Circuits for Biomedical Applications
Biomedical and healthcare applications provide attractive opportunities for the semiconductor sector. In both fields, the target is to gather data from multiple sensor nodes with minimal power consumption while maintaining low noise operation. However, designing a sensor interface circuit for such applications is challenging due to its harsh environment. Also, in such cases, the trade-off between available resources and performance among the components both in analog front-end and in the digital back-end is crucial.
This talk will cover the design strategies of sensor interface circuits. Starting from a basic op-amp, we will first explore the difficulties, limitations, and potential pitfalls in sensor interface, and strategy to overcome such issues. Low noise operation leads to two dynamic offset compensation techniques, auto-zeroing, and chopper stabilization. After that, system-level considerations for better key metrics such as energy efficiency will be introduced. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. We will then see how the signal analysis part impacts the analog sensor interface circuit design. The lecture will conclude with interesting aspects and opportunities that lie ahead.
On-Chip Epilepsy Detection: Where Machine Learning Meets Patient-Specific Wearable Healthcare
Epilepsy is a severe and chronic neurological disorder that affects over 65 million people worldwide. Yet current seizure/epilepsy detection and treatment mainly rely on a physician interviewing the subject, which is not effective in infant/children group. Moreover, patient-to-patient and age-to-age variation on seizure pattern make such detection particularly challenging. To expand the beneficiary group to even infants and also to effectively adapt to each patient, a wearable form-factor, the patient-specific system with machine learning is of crucial. However, the wearable environment is challenging for circuit designers due to unstable skin-electrode interface, huge mismatch, and static/dynamic offset.
This lecture will cover the design strategies of patient-specific epilepsy detection System-on-Chip (SoC). We will first explore the difficulties, limitations, and potential pitfalls in wearable interface circuit design and strategies to overcome such issues. Starting from a one op-amp instrumentation amplifier (IA), we will cover various IA circuit topologies and their key metrics to deal with offset compensation. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. Moving on, we will cover the feature extraction and the patient-specific and patient-independent classification using Machine Learning technique. Finally, an on-chip epilepsy detection and recording sensor SoC will be presented, which integrates all the components covered during the lecture. The lecture will conclude with interesting aspects and opportunities that lie ahead.
Towards Monolithic Mobile Ultrasound Imaging System for Medical and Drone Applications
Ultrasound Imaging System (UIS) has been widely used in medical imaging with its non-invasive, non-destructive monitoring nature; but so far the UIS has large form factor, making it difficult to integrate in mobile form factor. For drone and robotic vision and navigation, low-power 3-D depth sensing with robust operations against strong/weak light and various weather conditions is crucial. CMOS image sensor (CIS) and light detection and ranging (LiDAR) can provide high-fidelity imaging. However, CIS lacks depth sensing and has difficulty in low light conditions. LiDAR is expensive with issues of dealing with strong direct interference sources. UIS, on the other hand, is robust in various weather and light conditions and is cost-effective. However, in air channel, it often suffers from long image reconstruction latency and low framerate.
To address these issues, this talk introduces UIS ASICs for medical and drone applications. The medical UIS ASIC is designed to transmit pulse and receive echo through a 36-channel 2-D piezoelectric Micromachined Ultrasound Transducer (pMUT) array. The 36-channel ASIC integrates a transmitter (TX), a receiver (RX), and an analog-to-digital converter (ADC) within the 250- μm pitch channel while consuming low-power and supporting calibration to compensate for the process variation of the pMUT. With its small form factor, Intervascular Ultrasound (IVUS) and Intracardiac Echocardiography (ICE) becomes a viable application. The ASIC in 0.18- μm 1P6M Standard CMOS is verified with both electrical and acoustic experiments with a 6×6 pMUT array. Also, the ASIC for drone applications generates 28 Vpp pulses in standard CMOS and the digital back-end (DBE) achieves 9.83M-FocalPoint/s throughput to effectively translate real-time 3-D image streaming at 24 frames/s. With an 8×8 bulk piezo transducer array, the UIS ASIC is installed on an entry-level consumer drone to demonstrate 7-m range detection while the drone is flying. The talk will conclude with interesting research directions lying ahead in UIS.
SSCS also maintains an Agreement of Cooperation with the IEEE Microwave Theory and Technology Society (MTT-S.) Their list of Distinguished Microwave Lecturers is available here.