Terms through 31 December 2026
Alphawave Semi and University of Toronto
Dr. Tony Chan Carusone has taught and researched integrated circuits and systems for high-speed connectivity in industry and academia for over 20 years. He has been the Chief Technology Officer of Alphawave Semi since 2022 and a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has received eleven best-paper awards at leading conferences for work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” and “Microelectronic Circuits,” the best-selling engineering textbook ever. He is a Fellow of the IEEE.
Presentations:
The Impact of Industry Trends on Wireline R&D
Abstract: Trends in high-performance computing and communication are creating new wireline connectivity demands. The increasing use of chiplets for AI computing and networking increases bandwidth demands in and out of the package and over die-to-die interfaces. Meanwhile, new paradigms for organizing computing within and between datacentres and across regional networks create new applications for optical data transmission. The resulting demands on the power, price and performance of transceiver circuits create new opportunities for innovation on high-performance analog front-ends, DSP, packaging, and optics.Talk Title #2: Scaling AI with Chiplet-Based Systems
Abstract: In the rapidly evolving landscape of artificial intelligence, chiplets are emerging as a transformative technology, paving the way for the next generation of AI systems. Chiplets permit the integration of more processing power within a single package, and allow for new connectivity solutions so that thousands of AI accelerators can work as a cohesive unit. Optical connectivity, facilitated by chiplets, offers high-speed data transmission with lower power consumption, crucial for handling the massive data loads in AI applications. The emerging chiplet ecosystem, underwritten by high-performance die-to-die interfaces, is throwing open the doors of innovation and facilitating the next wave of AI scaling.
Carnegie Mellon University
Vanessa Chen (Senior Member, IEEE) earned her Ph.D. in electrical and computer engineering from Carnegie Mellon University in 2013. Before joining Carnegie Mellon University as an Assistant Professor, she was affiliated with The Ohio State University. During her doctoral studies at Carnegie Mellon from 2010 to 2013, she conducted research on algorithm-assisted approaches for improving energy efficiency and ultra-high-speed ADCs with on-chip real-time calibration, and interned at IBM T. J. Watson Research Center in 2012. Prior to academia, she held positions as a circuit designer at Qualcomm in San Diego and Realtek, Hsinchu, Taiwan, focusing on self-healing RF/Mixed-signal circuits. Her research focuses on AI-enhanced circuits and systems, which include intelligent sensory interfaces, RF/mixed-signal hardware security, and ubiquitous sensing and computing systems. Dr. Chen has received the NSF CAREER Award, the IBM Ph.D. Fellowship, and the Analog Devices Outstanding Student Designer Award. She has been involved in various technical program committees, including the IEEE International Solid-State Circuits Conference (ISSCC), the IEEE Symposium on VLSI Circuits, the IEEE Custom Integrated Circuits Conference (CICC), the IEEE Asian Solid-State Circuits Conference (A-SSCC), and the IEEE/ACM Design Automation Conference (DAC). She also has served as an Associate Editor for several IEEE journals, including IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), IEEE Open Journal of Circuits and Systems (OJCAS). Additionally, she has contributed as a Guest Editor for the ACM Journal on Emerging Technologies in Computing Systems (JETC).
Presentations:
AI-Enhanced RF/Mixed-Signal Circuits for Extreme Environments
Abstract: AI-driven design and optimization are transforming RF and mixed-signal circuits for extreme environments, such as high-radiation, cryogenic, and high-temperature conditions. This work explores reinforcement learning (RL) and generative models to enhance circuit robustness and adaptability. RL-based self-healing mechanisms leverage embedded sensors for real-time monitoring and dynamic recovery, while generative models accelerate design space exploration, enabling resilient and efficient circuit topologies. By integrating AI with adaptive hardware architectures, this approach enhances performance and reliability in harsh-environment applications.High-Speed Analog-to-Digital Data Converters
Abstract: High-speed analog-to-digital converters (ADCs) are critical for modern communication, computing, and sensing systems, demanding high-efficiency and fast conversion rates. This presentation explores advanced architectures, circuit techniques, and design optimizations to enhance ADC performance. Emphasis is placed on high-speed sampling, low-jitter clocking, and energy-efficient quantization techniques. Novel calibration and AI-enhanced methods further improve linearity and robustness, enabling next-generation high-speed data conversion for high-performance applications.Wireless Security for IoT Systems: RF Fingerprinting, Authentication, and Encryption
Abstract: As IoT systems become increasingly pervasive, ensuring secure wireless communication is critical to prevent unauthorized access and cyber threats. This presentation explores advanced techniques for wireless security, including RF fingerprinting for device identification, lightweight authentication protocols, and efficient encryption schemes tailored for resource-constrained IoT devices. By leveraging in-sensor machine learning, RF fingerprinting enhances security by uniquely identifying devices based on inherent hardware variations. Combined with robust authentication and encryption, these techniques strengthen IoT resilience against spoofing, eavesdropping, and other attacks, ensuring reliable and secure wireless connectivity.
CalTech
Azita Emami is the Andrew and Peggy Cherng Professor of Electrical Engineering and Medical Engineering, and the Director of Center for Sensing to Intelligence (S2I) at Caltech. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively, and her B.S. degree from Sharif University of Technology in 1996. From 2004 to 2006 she was with IBM T. J. Watson Research Center before joining Caltech in 2007. She served as the Executive Officer (Department Head) for Electrical Engineering from 2018 to 2024. Her current research interests include integrated circuits and systems, integrated photonics, high-speed data communication systems, wearable and implantable devices for neural recording, neural stimulation, sensing and drug delivery.
Presentations:
Brain-Computer Interfaces: A Software-Hardware Co-Design Approach
Abstract: Brain-Computer Interfaces (BCIs) are technologies that communicate directly with the brain, and can improve the quality of life of millions of people with brain circuit disorders. Motor BCIs are among the most powerful examples of BCI technology, where microelectrode arrays are implanted into motor regions of tetraplegic participants. Movement intentions are decoded from recorded neural signals into command signals to control a computer cursor or a robotic limb. However, these systems fail to deliver the precision, speed, degrees of freedom and robustness of control enjoyed by motor-intact individuals. To enhance the overall performance of the BCI systems and to extend the lifetime of the implants, newer approaches for recovering functional information of the brain are necessary. To infer intent, BCI must extract features that accurately estimate neural activity. However, the degradation of signal quality over time hinders the use of standard techniques. In this presentation, we show that a convolutional neural network can be used to map electrical signals to neural features by jointly optimizing feature extraction and decoding under the constraint that all the electrodes must use the same neural-network parameters. In all human participants, our proposed neural network led to significant offline and online performance improvements in a cursor-control task across all metrics, outperforming the rate of threshold crossings and wavelet decomposition of the broadband neural data (among other feature-extraction techniques). We will show that the trained neural network can be used without modification for new datasets, brain areas and participants. We will also discuss software-hardware co-design approaches for energy-efficient hardware implementation of learning-based BCI systems towards miniaturized implantable and wearable devices.Electronic-Photonic Co-Design for High-Speed Data Communication and Beyond
Abstract: Data centers continue to demand interconnect solutions with higher bandwidth densities and improved energy efficiency. Furthermore, applications such as chip-to-chip interconnects in switches, high-performance FPGAs and GPUs call for compact form-factors, high-volume production and low-cost. Silicon Photonics (SiP)-based transceivers, when co-packaged with CMOS electronics, offer a promising avenue to meet these demands with speeds exceeding 100 Gb/s per wavelength. In this talk we focus on architectural and circuit-level techniques for both PICs and EICs to improve the energy-efficiency at high data rates. We will discuss how various types of optical modulators and optical architectures can be employed to achieve higher-order modulation schemes. We will first present a 100Gb/s 3D integrated Sip-CMOS PAM4 optical transmitter system. The photonic chip includes a push-pull segmented MZM structure using highly capacitive, yet optically efficient MOSCAP phase modulators. Co-design and optimum bandwidth enhancement techniques are employed to achieve high data rates and energy efficiency. Next a 100Gb/s DAC-less PAM-4 transmitter and a 200Gb/s QAM-16 transmitter in a multi-micron silicon photonics platform using binary-driven SiGe EAMs will be presented. In the second part of this talk, we will briefly show another example of co-designed electronics and photonics for sensing applications. We present a fully integrated fluorescence (FL) sensor in 65nm standard CMOS comprising on-chip bandpass optical filters, photodiodes (PDs), and processing circuitry. The metal/dielectric layers in CMOS are employed to implement low-loss cavity-type optical filters achieving a bandpass response at 600nm to 700nm range suitable to work with fluorescent proteins (FPs), which are the widely used bio-reporters for biomedical and environmental sensing.Wireless Medical Devices for Sensing and Navigation
Abstract: Microscale implantable and wearable devices will transform the field of medicine in the near future. This talk will focus on design and implementation of miniaturized minimally invasive devices for continuous monitoring and closed-loop therapeutic systems. In the first part of this talk, an MRI-inspired approach for precise localization and tracking of small tags, smart pills and sensors inside the body will be presented. The prototype devices called ATOMS (Addressable Transmitters Operated as Magnetic Spins) are designed to behave similar to real atoms in the body without the need for the strong magnetic field of MRI. We will also show how these devices can be used for 3D navigation during high-precision surgeries. As part of this work, we will present a novel 3-D magnetic sensor in CMOS with high-resolution and ultralow-power operation. The sensor was successfully used for 3-D localization and tracking of catheters with 500-µm mean accuracy in a surgical operation room. In the second part of this talk, we will discuss miniaturized multi-modal wearable and implantable biosensors. In particular we will focus on energy harvesting techniques for such applications. I addition to wireless RF energy harvesting, a biofuel-cell-based energy harvester with 86% peak efficiency and 0.25V minimum input voltage using source-adaptive MPPT will be presented.
KU Leuven
Georges G.E. Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven (KU Leuven), Belgium, in 1986 and 1990, respectively. Currently, he is Full Professor in the MICAS research division at the Department of Electrical Engineering (ESAT) at KU Leuven. From August 2013 until July 2017 he served as Vice-Rector for the Group of Sciences, Engineering and Technology. In 2018 he was visiting professor at UC Berkeley and Stanford University. From 2020 to 2024 he served as Chair of the Department of Electrical Engineering (ESAT) at KU Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation, including modeling, simulation, optimization and synthesis as well as testing. He is a frequently invited speaker/lecturer and coordinator/partner of several (industrial) research projects in this area, including an ERC Advanced Grant. He has (co-)authored 10 books and more than 700 publications in edited books, international journals and conference proceedings. He is a 1997 Laureate of the Belgian Royal Academy of Sciences, Literature and Arts in the discipline of Engineering. He is Fellow of the IEEE since 2002, and received the IEEE CAS Mac Van Valkenburg award in 2015 and the IEEE CAS Charles Desoer award in 2020, as well as the EDAA Achievement Award in 2021. He is an elected member of the Royal Flemish Academy of Belgium in the class of Technical Sciences, and of the Academia Europaea.
Presentations:
Who will design tomorrow’s analog integrated circuits: humans or AI-based synthesis?
Abstract: Analog/mixed-signal integrated circuits are key in applications where electronics interface with the physical world. The design of analog circuits, however, is time consuming and prone to errors, often requiring multiple redesign cycles. The rebirth of AI and machine learning, and the recent rise of generative AI methods, on the other hand, create a whole new spectrum of techniques to automate this process. This invited talk will explore the high potential of using advanced machine learning (ML) techniques to automatically synthesize and lay out analog integrated circuits. What is hype and what will be feasible? Will we still need analog designers in the future and how will they operate?Designing analog functions without analog circuits
Abstract: The continuous progress of CMOS semiconductor technology fuels the ongoing digitization in our daily life. Yet, analog/mixed-signal integrated circuits are key in applications where electronics interface with the physical world. This presentation focuses on core challenges in the design of such analog interfaces, where low cost, low power consumption and high reliability are major targets besides raw performance. Key to achieving solutions with small area (cost) and low power is to design the analog functions in a highly digital manner, i.e. without actual analog circuits. This will be illustrated with several practical design examples for sensor interface readout and data conversion circuits for applications such as automotive and biomedical.
Massachusetts Institute of Technology
Ruonan Han is a Professor in the Electrical Engineering and Computer Science Department at MIT. His research group focuses on RF-to-photonics integrated systems for spectroscopy, metrology, imaging, quantum sensing/ processing, broadband/secure communication, etc. His recent awards include the National Science Foundation CAREER Award in 2017, the Intel Outstanding Researcher Award in 2019, the IEEE MTT-S Distinguished Microwave Lecturer in 2020-2022, the IEEE SSCS New Frontier Award in 2023, and three IEEE RFIC Symposium Best Student Paper Awards in 2012, 2017 and 2021. He currently serves as the Associate Director of MIT’s Microsystem Technology Laboratories (MTL), and the Director of MIT/MTL Center of Integrated Circuits and Systems. Ruonan is the TPC member of ISSCC and RFIC, as well as an Associate Editor of the IEEE Open Journal of the Solid-State Circuits Society. Ruonan received his B.S. degree in Microelectronics from Fudan University in 2007, M.S. degree in Electrical Engineering from the University of Florida in 2010, and Ph.D. degree in Electrical and Computer Engineering (with Cornell ECE Best PhD Thesis Award) from Cornell University in 2014.
Presentations:
Emerging Chip-Scale Terahertz Systems for Sensing, Metrology and Security Applications
Abstract: Terahertz (THz) electronics is attracting increasing attentions due to the recent “beyond-5G” research. On the other hand, it may surprise many that devices for THz wave generation and detection had in fact been reported as early as one century ago, and even the CMOS-based low-cost THz circuit also already has more than 15 years of history. Despite those advances, exploration of unique and practical applications of the THz technology, especially the applications for THz chip-scale systems, is still far from enough. In this talk, we introduce some recent research outcomes in this regard. Showcased prototypes include high-angular-resolution radars, ultra-miniaturized and unclonable RFIDs, molecular spectrometer-based gas sensors and clocks, low-heat-load cryogenic interconnects, among others.Chip-Scale Wave-Matter Interactions at RF-to-Light Frequencies: Circuits, Systems and Applications
Abstract: Traditional EM spectral sensors using integrated circuit technologies (e.g. automotive radars, security imagers, cameras, etc.) are normally based on wave scattering or absorption by macroscopic objects at remote distance; the operations are also not specific in wave frequencies. In the past couple of years, a new paradigm of chip-scale EM spectral sensing emerges with features complementary to the above: they utilize various modalities of interactions between EM waves with high-precision frequency control and microscopic particles (molecules, atoms, etc.) in close proximity to the chip. This progress is enabled by the recent advances of silicon devices and processes, especially the increase of circuit operation frequencies into the terahertz regime. Chip-scale sensing and metrology systems with new capabilities, higher performance and unprecedented affordability now become possible. Examples include THz gas spectroscopy sensors, on-chip “atomic-clock-grade” frequency references, room-temperature CMOS-quantum magnetometers, etc. This talk will present the basic physics of a few types of wave-matter interactions, key enabling technologies, as well as the designs and prototypes of chip systems. We will also discuss their potential applications in bio-chemical analysis, wireless networks, PNT (positioning, navigation & timing), security and so on.
University of Illinois, Urbana-Champaign
Pavan Hanumolu is a Professor in the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. He received a Ph.D. from the School of Electrical Engineering and Computer Science at Oregon State University in 2006, where he subsequently served as a faculty member until 2013. Dr. Hanumolu’s research interests include energy-efficient integrated circuit implementation of analog and digital signal processing, frequency references, wireline communication systems, and power conversion. He served as the Editor-in-Chief of the IEEE Journal of Solid-State Circuits and is an IEEE Fellow.
Presentations:
Energy-Efficient and Fully Integrated Frequency References: Overcoming Stability and Accuracy Challenges
Abstract: Reliable frequency references are essential for various applications, from precise timekeeping in calendar functions to stable clocks for radios and microcontrollers. While quartz crystal-based references deliver excellent performance, their bulk and incompatibility with monolithic integration limit their scalability. In this talk, I will explore techniques for realizing fully integrated frequency references that are both energy-efficient and highly stable across temperature, voltage, and process variations. I will discuss advanced methods to enhance the frequency accuracy of RC oscillators through precise cancellation of resistor temperature coefficient across PVT variations. Additionally, I will examine the long-term impact of component aging on frequency stability and present practical strategies to mitigate its effects.
Associate Professor, Eindhoven University of Technology
Pieter Harpe (SM'15) received the MSc and PhD degrees from the Eindhoven University of Technology, The Netherlands, in 2004 and 2010, respectively. In 2008, he started as researcher at Holst Centre / imec, The Netherlands, where he worked on ultra low-power wireless transceivers, with a focus on ADC research and design. In April 2011, he joined Eindhoven University of Technology where he is currently an Associate Professor and lead of the Resource Efficient Electronics Lab. His main activities are on low-power analog and mixed-signal circuits, for instance for biomedical applications, internet of things, and edge AI. Dr. Harpe is TPC member for ISSCC and A-SSCC, Associate Editor for TCAS-I, SSCS AdCom Member-at-Large and SSCS Distinguished Lecturer. He previously served as TPC member for ISSCC, TPC member and track chair for ESSCIRC/ESSERC and co-organizer for AACD, was an IEEE SSCS Distinguished Lecturer in 2016/2017, and is recipient of the ISSCC 2015 Distinguished Technical Paper Award.
Presentations:
ADC Enhancement Techniques in Advanced CMOS Technologies
Abstract:The aim of this presentation is to introduce the basics and various practical illustrations of advanced ADC enhancement techniques in a nutshell. With applications pushing for higher resolutions & data-rates, and technology-scaling favoring digital design, the use of digital techniques to enhance ADC performance is inevitable. This talk will first summarize trends and trade-offs regarding the use of these digital-intensive techniques before illustrating some popular and recent examples from literature, including calibration and enhancement techniques as well as digitally-inspired analog circuit design. Besides that, an outlook is given regarding future challenges and opportunities in advanced CMOS technologies.Energy Efficient ADC Design Techniques
Abstract:In this review presentation, we will have a look at ADC efficiency trends over the years as function of ADC architecture, resolution, and sampling rate. After that, state-of-the-art design examples from literature are reviewed, and the key techniques to achieve high efficiency are highlighted. This includes techniques at circuit, system, layout and algorithmic levels. ADC architectures such as Pipelined, Sigma-Delta, SAR, Noise-Shaping SAR, and others are all briefly covered. The presentation concludes with a reflection on the differences and similarities of the highlighted efficiency features.ADC Innovations for Improved Resolution, Power and Form Factor
Abstract:ADC design is progressing rapidly over time thanks to innovations in architecture, circuit implementation, and technology scaling. For many emerging applications, for instance in the field of IoT or medical devices, converters with high resolution, low power consumption, and a small form factor are desired. In this tutorial-level presentation, we will explain the general trade-offs for these performance metrics, and we will highlight some of the recent developments that pushed the state-of-the-art forward. The talk will also give some insight into the challenges when embedding converters in an overall system.Ultra low power SAR ADCs and versatile, dynamic sensor interfaces
Abstract:In this talk, we will take a look at ultra low power sensor interfaces for IoT applications. In such applications, the sensing operation is often done at a relatively low frequency, and sometimes it is heavily duty-cycled, or it should be triggered by particular events or thresholds. For that reason, dynamic operation is beneficial as compared to static operation. We will review ADC and sensor interface architectures that can operate dynamically and that can be triggered by a single clock pulse. Various capacitive and resistive sensor interfaces are shown, and the final example shows a resistive-based temperature sensor interface including analog correction techniques for gain, offset and distortion.
University of Tokyo
Tetsuya Iizuka received B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was a high-speed serial interface circuit engineer with THine Electronics Inc., Tokyo, Japan. He joined the University of Tokyo in 2009, where he is currently an Associate Professor with Systems Design Lab., School of Engineering. From 2013 to 2015, he was a Visiting Scholar at the University of California, Los Angeles, CA, USA. His current research interests include data conversion and frequency synthesis techniques, high-speed analog integrated circuits, digitally-assisted analog circuits, and VLSI computer-aided design. He was a member of the IEEE International Solid-State Circuits Conference (ISSCC) Technical Program Committee from 2013 to 2017 and the IEEE Custom Integrated Circuits Conference (CICC) Technical Program Committee from 2014 to 2019. He is currently serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and IEEE VLSI Symposium on Circuits Technical Program Committees. He is a recipient of the 21st Marubun Research Encouragement Commendation from the Marubun Research Promotion Foundation in 2018, the 13th Wakashachi Encouragement Award First Prize in 2019, and the 18th Funai Academic Prize from the Funai Foundation for Information Technology in 2019. He is a co-recipient of the IEEE International Test Conference Ned Kornfield Best Paper Award in 2016.
Presentation(s):
Systematic Equation-Based Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW
Abstract: As data converters find their way into virtually every microelectronic device, developers of application-specific systems-on-a-chip increasingly suffer from large development costs arising from limited specialized design expertise and the tedious process of migration to new technology nodes. In this talk, we introduce three pieces of analysis for the optimum design of key building blocks in the ADC: a) Distortion and bandwidth of a passive sample and hold (S/H) circuit, b) noise and offset of a regenerative comparator, and c) jitter analysis for a clock distribution path. By deploying these analysis tools, a systematic design framework of ADCs is demonstrated with the optimized design of a self-timed charge-redistribution SAR ADC.Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
KAIST
Minkyu Je received his B.S., M.S., and Ph.D. degrees in Electrical Engineering and Computer Science from KAIST, Daejeon, Korea, in 1996, 1998 and 2003, respectively. In 2003, he joined Samsung Electronics, Korea, as a Senior Engineer. From 2006 to 2013, he was with IME, A*STAR, Singapore. From 2011 to 2013, he led the Integrated Circuits and Systems Laboratory at IME as a Department Head. He also served as Program Director of the NeuroDevices Program under A*STAR SERC from 2011 to 2013. He was an Associate Professor at DGIST, Korea, from 2014 to 2015. Since 2016, he has been an Associate Professor in the School of Electrical Engineering at KAIST, Korea. His research includes the development of advanced IC platforms for smart sensor interfaces, low-power wireless communication, high-efficiency energy supply and management, low-power timing, and resource-constrained computing. He also works on microsystem integration, leveraging these IC platforms for emerging applications such as intelligent miniature biomedical devices, ubiquitous wireless sensor nodes, and future mobile devices. He is an editor of one book, an author of seven book chapters, and has more than 430 peer-reviewed international conference and journal publications. He also has more than 80 patents, either issued or filed. He has served on the Technical Program Committee and Organizing Committee of various international conferences, symposiums, and workshops, including IEEE ISSCC, A-SSCC, SOVC, ISCAS, and BioCAS. He was a Distinguished Lecturer of the IEEE CASS from 2020 to 2022 and is currently serving as an Associate Editor of IEEE TBioCAS. He was awarded the Haedong Semiconductor Engineering Award in 2022 and received the Ministerial Commendation from the Ministry of Science and ICT in 2024.
Presentations:
Capacitance-to-Digital Converters (CDCs), Interfacing with Capacitive Sensors
Abstract: Capacitive sensors are extensively utilized for IoT applications due to their low noise and temperature dependence. They find can be used to sense a broad range of physical quantities, such as pressure, humidity, acceleration, gas molecules, and proximity. To read out such sensors and extract useful information, high performance capacitance-to-digital converters (CDCs) are required. Their design is challenging due to the many design tradeoffs that must be made between performance parameters such as energy efficiency, sensing resolution, and input range. In this talk, the basic principles of capacitive sensors, the design goals and tradeoffs of CDCs, and conventional circuit structures will first be reviewed. Then, more recent and advanced circuit structures and design techniques to improve energy efficiency, sensing resolution, and input range will be presented. Lastly, some future research directions in the design and application of CDCs will be discussed.Process-Scalable Low-Power Amplifiers
Abstract: Dynamic amplifiers have received increasing interest in state-of-the-art systems due to their superior power efficiency and scalability with technology. They have, for example, found many applications in low-power ADCs as error/residue amplifiers or loop filters. This talk will introduce various types of dynamic and ring amplifiers. Their conventional structures and basic operational principles will be explained, and a diverse range of topologies, as well as corresponding design tradeoffs, will be described. The effects of PVT variations on their performance and design considerations will also be discussed. Through this tutorial, attendees will obtain a solid understanding of the basics of dynamic and ring amplifiers, including design choices, tradeoffs, and considerations, along with an overview of recent developments.Low-Power Bioimpedance Measurement Techniques for Sensing and Imaging
Abstract: Bioimpedance measurement is one of key methods to interface with biology and finds a very wide range of sensing and imaging applications, including body composition analysis, cardiovascular monitoring, respiratory monitoring, detection of tissue abnormalities, characterization of tumor progression, neural activity monitoring, and functional localization of peripheral nerves. In this talk, the basic principles of bioimpedance measurement and the overall circuit system structure composed of an excitation signal generation circuit block and an impedance readout circuit block will be reviewed first. Then, the design goals, challenges, and tradeoffs of such circuit blocks and integrated systems will be explained. Also, various design techniques that have been proposed to improve diverse performance parameters, such as energy efficiency, measurement accuracy, resolution, dynamic range, frequency coverage, and throughput, will be introduced and discussed with the foremost focus on the low-power design aspect, which is essential for battery-powered or battery-less systems.Building Neural Interfaces: Key Components, System Integration, and Technical Hurdles
Abstract: Implantable neural interface systems are widely used for neurotherapeutics to treat neurological disorders and neuroprosthetics to restore neurologically impaired body functions. In this talk, after introducing a generic structure of fully implantable neural interface systems, we investigate how this structure is varied when used for different applications. Then, the challenges faced in developing key components of the system, such as neural recording and stimulation, wireless power transfer, wireless data communication, and signal processing, are explained, followed by the discussion of system integration challenges. Lastly, recently reported neural interface system examples are introduced to showcase how researchers are trying to address those challenges.
Columbia University
Peter Kinget is the Bernard J. Lechner Professor of Electrical Engineering at Columbia University in New York. His research group focusses on the design of analog and RF integrated circuits and the novel systems or applications they enable in communications, sensing, computing, and power management. He also devotes a lot of his energy to teaching initiatives like https://mosbius.org and https://vlsidesignlab.org He received his engineering and Ph.D. degrees in electrical engineering from the Katholieke Universiteit in Leuven (Belgium). He has worked in industrial research and development at Bell Laboratories, Broadcom, Celight and Multilink before joining the faculty of the Department of Electrical Engineering, Columbia University, NY in 2002. He served as Department Chair from 2017 to 2020. He is also a consulting expert on patent litigation and a technical consultant to industry. Peter is a Fellow of the IEEE and is widely published. He received several awards including the "IEEE Solid-State Circuits Society 2020 Innovative Education Award and the “2011 IEEE Communications Society Award for Advances in Communication” (for an outstanding paper in any IEEE Communications Society publication in the past 15 years). He is a “Distinguished Lecturer” for the IEEE Solid-State Circuits Society (SSCS), and has been an Associate Editor of the IEEE Journal of Solid State Circuits (2003-2007) and the IEEE Transactions on Circuits and Systems II (2008-2009). He has served on the program committees of many of the major solid-state circuits conferences and has been an elected member of the IEEE SSCS Adcom (2011-2013 & 2014-2016).
Presentations:
Circuit Labs at the Lunch Table with MOSbius
Abstract: Learning integrated circuit design requires gaining a broad range of skills and knowledge including circuit analysis and design, signals & systems, applied electro-magnetics, and semiconductor physics. Learning theory has always been most accessible through books or now the internet. Simulation tools are now also widely available on personal computers, including open-source versions. But, learning measurements so far has been mostly confined to school or industry laboratories. Yet, physical intuition and practical experience keeps playing a significant role in the development of successful, high performance integrated circuits. We will present the MOSbius platform that allows a student or designer to experiment with IC-style, analog, CMOS circuits at the lunch table. This unique platform uses a custom chip with CMOS building blocks that can be wired on a breadboard or with a programmable on-chip switch matrix. Measurements can be conducted using an affordable, all-in-one, USB lab instrument. Ready-to-go experiments are provided to learners and instructors on https://mosbius.org. Nothing can substitute for the aha moment when you observe a circuit finally working. The debugging process to bring-up the circuit teaches the designer essential lessons that carry over to high performance circuits in highly scaled technologies. The MOSbius platform aims to make lab experience widely accessible and affordable to learners.Teaching IC Design: From Concepts to Testing a Fabricated Custom Chip
Abstract: In this talk I will share my experience of developing the VLSI Design Lab (https://vlsidesignlab.org) at Columbia University, a class where students define an integrated circuit; design, simulate, and lay it out; have the chip fabricated; and test and demonstrate their chip in an application. The lab offers a holistic experience not only of the chip design process, but also of integrating the chip in an application. It exposes students to many topics that are often overlooked in lecture or simulation-based courses. The lab has been taught six times and more than 55 chips have been taped out by more than 140 students. Popular designs include class-D audio amplifiers, PPG-based monitors, digital clocks, or ultrasound transceivers; we have also built a RISC-V processor, neural processing units, an FPGA, ADCs and RF circuits. I will discuss the unique educational benefits that students gain from this type of course. Whereas the logistics of offering a lab like this might look daunting, there are many tools and services available that along with careful organization and scheduling make it possible.
Intel Corporation
Dr. Ram K. Krishnamurthy is Intel Fellow at Intel Corporation, Intel Labs, Office of the CTO. In this role, he is responsible for research in high performance energy efficient integrated circuits for future CPUs, GPUs, AI processors and accelerators across data center to edge computing platforms. He has 27+ years of experience and deep expertise in Systems-on-Chip (SOC) design in leading-edge semiconductor technologies. Since 1997, he led circuit technology research and made major contributions to Intel data center, client, GPU, FPGA, edge IoT, and AI products portfolio spanning twelve generations of silicon processes. Dr. Krishnamurthy has filed more than 350 patents and holds over 200 issued patents. He has published 200 papers in premier IEEE conferences and journals. He is a recipient of two Intel Achievement Awards (Intel Corporation’s highest technical award), Intel Labs Gordon Moore Award, Intel inventor awards for highest number of patents filed and issued, Distinguished paper award from IEEE International Solid State Circuits Conference, Outstanding industry mentor award from Semiconductor Research Corporation, Best paper award from IEEE European Solid State Circuits Conference, Distinguished alumni award from State University of New York, Alumni recognition award from Carnegie Mellon University, and MIT Technology Review TR35 innovator award. He was recognized as a top contributor in IEEE International Solid State Circuits Conference’s 70 years publication history. He is a Fellow of the IEEE. Dr. Krishnamurthy served as Chair of Semiconductor Research Corporation Technical Advisory Board AMS-CSD. He was General Chair and Technical Program Chair of IEEE International Systems-on-Chip Conference and is currently on the Steering Committee. He served as guest editor of the IEEE Journal of Solid State Circuits, associate editor of the IEEE Transactions on VLSI Systems, and on the technical program committees of ISSCC, CICC, ESSCIRC, and SOCC conferences. He was distinguished lecturer of IEEE Solid State Circuits Society and adjunct faculty of electrical and computer engineering at Oregon State University, where he taught advanced VLSI design. He is a board member on various industry advisory boards. Dr. Krishnamurthy received the B.E. degree in electrical engineering from National Institute of Technology, Trichy, India, in 1993, M.S. degree in electrical and computer engineering from State University of New York at Buffalo in 1994, and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 1997.
Presentation:
High-performance Energy-efficient Compute-in-Memory and AI accelerators for sub-18A Technologies
Abstract: This presentation will highlight some of the emerging challenges and opportunities for sub-18A process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-18A technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for digital and analog in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
Intel
Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as Distinguished Lecturer. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents and recently received the ISSCC 2024 Outstanding Forum Speaker Award.
Presentation:
The Road to Gate-All-Around and Its Impact on Analog Design
Abstract: Despite the much debate end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesized by Gordon Moore's seminal 1965 paper.
Delft University of Technology
Kofi A.A. Makinwa received the B.Sc. and M.Sc. degrees from Obafemi Awolowo University, Ife, Nigeria, the M.E.E. degree from the Philips International Institute, Eindhoven, The Netherlands and the Ph.D. degree from Delft University of Technology, Delft, The Netherlands. From 1989 to 1999, he was a Research Scientist with Philips Research Laboratories, Eindhoven, The Netherlands. Since 1999, he has been at Delft University of Technology, where he is now the Head of the Microelectronics Department. His research interests include the design of mixed-signal circuits, sensor interfaces and smart sensors. This has resulted in 20+ books, 350+ technical papers, and 40+ patents. Dr. Makinwa has served on the program committees of several IEEE conferences, including the ISSCC, where he was the Analog Subcom chair from 2018 to 2021. He has also been an elected member of the Adcom of the Solid-State Circuits Society. He is currently a distinguished lecturer of the Solid-State Circuits Society, a member of the ExCom of the VLSI Symposium, and a member of the program committees of the Advances in Analog Circuit Design (AACD) workshop and the IEEE Sensor Interfaces Meeting (SIM). Dr. Makinwa is the co-recipient of 18 best paper awards, from the JSSC, ISSCC and VLSI symposium, among others. At the 70th anniversary of ISSCC, he was recognized as its top contributor with 70+ papers. He is an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences.
Presentations:
Precision CMOS Amplifiers
Abstract: In CMOS, mismatch is a fact of life! In amplifiers, it causes offset voltages of a few millivolts and gain error of a few percent. However, amplifier performance can be dramatically improved by the application of dynamic techniques such as auto-zeroing, chopping and dynamic element matching. Offset can be reduced to the microvolt level and gain errors less than 0.1% can be achieved in standard CMOS. Compared to the alternatives, i.e. the use of huge devices or trimming, the use of dynamic techniques has the added advantage of also reducing 1/f noise and drift, making it possible to design amplifiers that are thermal-noise limited. In this tutorial, an introduction to auto-zeroing, chopping and dynamic element matching will be given, their pros and cons highlighted and recent advances in the state-of-the-art reviewed.Smart Sensors in Standard CMOS
Abstract: Sensors are everywhere! Temperature sensors throttle SoCs, accelerometers activate airbags, and gyroscopes and magnetometers are now standard smart phone components. These are all examples of smart sensors, i.e. sensors that are co-integrated with their readout electronics and so provide digital output. However, processing the weak analog output of typical sensors is quite challenging, especially when it must be done in standard CMOS, whose precision is limited by 1/f noise, component tolerances and mismatch. In this tutorial, a system approach to the design of smart sensors will be presented. The use of dynamic techniques, such as chopping, auto-zeroing, dynamic element matching and sigma-delta modulation, to trade speed for precision will be discussed. The proposed methodology will be illustrated by case studies describing the design of state-of-the-art CMOS sensors for the measurement of wind velocity, magnetic field and temperature.The Zoom ADC: An Evolving Architecture
Abstract: Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (ΔΣM) to efficiently achieve high resolution and dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This talk presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 μm technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only a few hundreds of μWs.Giving Great Technical Talks
Abstract: Technical ideas only become impactful if they are effectively communicated. The bad news is that most engineers are not natural communicators. The good news, though, is that most of them can learn how to become good communicators. In this talk, I will share a few guidelines to better presentations, based on over 20 years of successfully helping my students and colleagues to give great technical talks.Precision Band-Gap Circuits: Less is More!
Abstract: The ubiquitous bandgap voltage reference is used in nearly every integrated circuit manufactured today. It also forms the heart of most integrated temperature sensors. Despite decades of use, however, recent research has shown that it is still possible to improve on the state-of-the-art by adhering to the old adage: less is more! By following this approach, voltage references and temperature sensors have been realized with relative inaccuracies as low as 0.15% over the military temperature range (-55C to 125C).
Intel
Carlos Tokunaga is a Principal Engineer at Intel Corporation and leads the Reliability and Resiliency Circuit Technology Group at the Circuit Research Lab. Carlos received the B.S. degree in electronics engineering from the University of Los Andes, Bogotá, Colombia, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2005 and 2008, respectively. He is an IEEE Senior Member and serves as a Member-at-Large in the IEEE SSCS Adcom. He currently serves as the TPC Chair for CICC and is a TPC member of ISSCC. He served in the VLSI Symposium TPC 2019-2024. He serves as an Associate Editor for the Open Journal of SSCS and is an SSCS Distinguished Lecturer. He received Intel Lab’s Gordon Moore Award in 2018. He has published over 50 technical papers in refereed conferences and journals and received 78 patents. Talks may be presented in English or Spanish.
Presentations:
Talks may be presented in English or Spanish.Circuits and Technology Advancements for Resiliency and Reliability
Abstract: Next-generation SoCs for the Zetta-Scale computing era will be developed with increased integration of our compute, memory and communication systems in optimized advanced packaging solutions. The complexity of these systems is growing exponentially and the need to increase reliability while achieving high energy-efficiency is paramount. We will explore the challenges and opportunities in technology, packaging and circuits to enable resilient and reliable circuits and systems. We will study several cases of advanced circuit design to address those growing challenges.The Awesome World Enabled by Semiconductors (INSPIRE Program)
Abstract: Semiconductors are pervasive in all aspects of society. We will explore the technological advancements that have led to the explosion of semiconductors in our world and look at different circuit applications that showcase that impact. We will also learn how the Solid-State Industry and our Society has shaped our field and the opportunities that we have to develop and grow the next generation of engineers.Terms through 31 December 2025
Qualcomm
Keith A. Bowman is a Principal Engineer and Manager in the System-on-Chip (SoC) Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC, USA. He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors. He pioneered the invention, design, and test of Qualcomm’s first commercially successful circuit for mitigating the adverse effects of supply voltage droops on processor performance, energy efficiency, and yield. He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering. From 2001 to 2013, he worked in the Technology Computer-Aided Design (CAD) Group and the Circuit Research Lab at Intel Corporation in Hillsboro, OR, USA. In 2013, he joined the Qualcomm Corporate Research and Development (CRD) Processor Research Team. Dr. Bowman has published 90+ technical papers in refereed conferences and journals, authored one book chapter, received 30+ US patents and 50+ international patents, and presented 50+ tutorials on variation-tolerant circuit designs. He received the 2016 Qualcomm CRD Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, for the pioneering invention of the auto-calibrating adaptive clock distribution circuit, which significantly enhances processor performance, energy efficiency, and yield and is integral to the success of the Qualcomm® Snapdragon™ 820 and future processors. He received the 2022 Qualcomm IP Achievement Award for high-quality inventions, leading to strong processor performance and energy-efficiency improvements and differentiated products. Since 2018, he served on the Qualcomm Low-Power Circuit Design Patent Review Board. In 2019 and 2020, he was as an IEEE SSCS Distinguished Lecturer (DL). He is currently serving a 2nd 2-year term as an IEEE SSCS DL. From 2020 to 2023, he served as an IEEE SSCS Mentor. He was the International Technical Program Committee (ITPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively. He has served on the ISSCC ITPC as a member of the Digital Circuits (DCT) Subcommittee from 2016 to 2020 and as the DCT Chair from 2020 to 2024. He currently serves as the ISSCC Program Vice Chair. He is a Fellow of the IEEE.
Presentation(s):
Adaptive Processor Designs
System-on-chip (SoC) processors across a wide range of market segments, including Internet of Things (IoT), mobile, laptop, automotive, and datacenter, experience dynamic device, circuit, and system parameter variations during the operational lifetime. These dynamic parameter variations, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations, degrade processor performance, energy efficiency, yield, and reliability. This lecture introduces the primary variation sources and the negative impact of these variations across voltage and clock frequency operating conditions. Then, this lecture presents adaptive processor designs to mitigate the adverse effects from dynamic parameter variations while highlighting the key trade-offs and considerations for product deployment.
Tsinghua University
Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. Currently he is with Tsinghua University, Beijing, China, as an Associate Professor. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications and radars systems. He has authored or co-authored more than 160 IEEE journal and conference articles. Dr. Deng is a Technical Program Committee (TPC) Member of ISSCC, VLSI, A-SSCC, CICC and ESSCIRC. He has been an Associate Editor and a Guest Editor of the IEEE Solid-State Circuits Letters (SSC-L), and a Guest Editor of the IEEE Journal of Solid-state Circuits (JSSC).
Presentation(s):
High-Performance PLLs: Evolution, Challenges, and Future Directions
High-performance phase-locked loop (PLL) is one of the key techniques for both communication and radar systems, which makes it to be the cutting-edge topic in the field of integrated circuit and system design. It involves various research directions such as mixed-signal circuit design, digital algorithms, and system-level architecture. This lecture will discuss the high-performance PLL circuit and architecture evolution, review the latest research progress and discuss the future development trends of high-performance PLLs, with particular emphasis on ultra-low jitter PLLs toward 10-fs.rms and FMCW PLLs with ultra-fast and linearized chirp in CMOS technology.Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design
Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. This lecture will introduce the current and future trends in the emerging joint radar-communication CMOS transceiver from system architecture to circuit design.
IBM T.J. Watson Research Center
Timothy O. (Tod) Dickson received dual B.Sc. degrees in electrical and computer engineering with highest honors from the University of Florida in 1999. He completed the M. Eng degree at the University of Florida in 2002 and the Ph.D. degree at the University of Toronto in 2006, both in electrical engineering. His Ph.D. work was in the area of serial transceivers operating up to 80 Gb/s in SiGe BiCMOS technologies, focusing on the development of low-noise and low-power design methodologies. In 2006, he joined the IBM T.J. Watson Research Center in Yorktown Heights, N.Y where he is currently a Principal Research Scientist. His research focuses on the design of high-speed, low-power serial transceivers for electrical and optical links. Since 2014, he has served on the Technical Advisory Board of the Semiconductor Research Corporation Analog-Mixed Signal Circuits, Systems, and Devices (AMS-CSD) thrust. He is also an Adjunct Professor at Columbia University, where he has taught graduate level courses in analog and mixed-signal integrated circuit design since 2007. Dr. Dickson has been a recipient or co-recipient of several best paper awards, including the Best Paper Award for the 2009 IEEE Journal of Solid-State Circuits, the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the Best Paper Award at the 2015 IEEE Custom Integrated Circuits Conference (CICC), and the Best Student Paper Award at the 2004 Symposium on VLSI Circuits He was a member of the Technical Program Committee (TPC) of the IEEE Compound Semiconductor Integrated Circuit Symposium from 2007-2009, and of the IEEE CICC from 2017-2023 where he chaired the wireline subcommittee. He was a guest editor of the October 2010 issue of the IEEE Journal of Solid-State Circuits. From 2018-2023, he was an Associate Editor for the IEEE Solid-State Circuits Letters. Since 2024 he has been an Associate Editor for the IEEE Open Journal of the Solid-State Circuits Society. He is an IEEE Senior Member
Presentation(s):
High-Speed DACs for 100+ Gb/s Wireline Links
Digital-to-analog converters (DACs) operating above 50GS/s are critical components of modern transmitters for wireline applications. These circuits permit data modulation and equalization to be moved from the analog domain (as was common in links operating below 50Gb/s) to the digital domain, thereby enabling today’s serial links operating at 100-200Gb/s. This lecture explores DAC design for wireline applications. Driver and multiplexer design techniques will be introduced, including those used for current-mode (CML) and voltage-mode (SST) drivers found in state-of-the-art serial links. As systems explore the use of more sophisticated modulation formats such as higher-order time domain pulse amplitude modulation (e.g., PAM6 or PAM8) or frequency domain modulation (e.g., OFDM), higher linearity DACs will be required than those employed in existing PAM4 systems. Techniques for adaptive calibration of DAC static linearity will be discussed. Designs of two different 8b DACs operating at 56 and 72GS/s in 7nm and 4nm FinFET technologies will be described as case studies.
IBM T. J. Watson Research Center
Dr. Daniel Friedman is currently a Distinguished Research Scientist and Senior Manager of the Communication Circuits and Systems department, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA; he is also an IEEE Fellow. He received his doctorate from Harvard University and then subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln Laboratory. At IBM, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include accelerator designs for AI, high-speed I/O design, phase-locked-loop design, millimeter-wave circuits and systems, and circuit/system approaches to enabling new computing paradigms, the latter including cryogenic electronics for use in quantum computing systems. He holds more than 90 patents and has authored or coauthored more than 85 publications. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 International Solid-State Circuits Conference (ISSCC), the 2009 Journal of Solid-State Circuits (JSSC) Best Paper Award (given in 2011), the 2017 ISSCC Lewis Winner Outstanding Paper Award, and the 2017 JSSC Best Paper Award (given in 2019). He has served on the technical program committees of the Bipolar Circuits and Technology Meeting (2003-2008) and of the ISSCC (2008-2016); since 2016, he has served as the ISSCC Short Course chair. He served as a member-at-large of the IEEE Solid-State Circuits Society (SSCS) Adcom from 2018-20, as the SSCS Distinguished Lecture chair from 2020 to 2021, and as Associate Editor of the JSSC from 2019-2023. He is the current Vice President of the SSCS.
Presentation(s):
AI accelerators and the chiplet paradigm
The growth in the application of machine learning and artificial intelligence technology to problems across virtually all spheres of endeavor has been and is expected to remain extraordinary. Hardware acceleration for machine learning tasks is a critical vector that has enabled this exceptionally rapid growth. Further accelerator advances are necessary to drive everything from improved efficiency for inference, to support ever-growing network sizes to improvements in support for network training, to enabling broadening of ML deployments across platforms with a wide range of power and performance envelopes. The emerging chiplet paradigm will drive not only the scaling of compute density in AI solutions, but also promises to enable a proliferation of customized AI solutions for a range of workloads. In this presentation, we will describe example AI accelerator designs in the context of a solution framework, how communication advances are linked AI accelerator advancement, and will discuss approaches to accelerate the emergence of a chiplet ecosystem, including how this emergence might drive new accelerator implementation opportunities.Cryogenic CMOS for future scaled quantum computing systems
Quantum computing represents a new paradigm that has the potential to transform problems that are computationally intractable today into solvable problems in the future. Significant advances in the last decade have lent support to the idea that quantum computers can be implemented, and further that the goal of demonstrating true performance advantages over traditional computing techniques on one or more problems may be achieved in the not so distant future. Delivering on this promise is expected to require quantum error correction solutions, in turn demanding large qubit counts that pose significant challenges for quantum computer implementations, especially in the area of qubit interface electronics. An active area of research to address this challenge is the use of integrated cryogenic CMOS designs. In this presentation, we will present a superconducting qubit-based quantum computing system framework, opportunities for cryogenic CMOS introduction into future systems, example cryogenic CMOS implementations and results, and next challenges that must be met to enable cryogenic CMOS adoption.
The University of Tokyo, Tokyo, Japan
Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor and director of Systems Design Lab(d.lab), the University of Tokyo. At the same time he has been involving the activities of VDEC(VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia. He worked for hardware security, asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain signal processing. He has been serving various positions of various international conferences, including ISSCC ITPC Chair(ISSCC 2021), IMMD sub-committee chair (ISSCC 2015-2018), A-SSCC 2015 TPC Chair, VLSI Circuits Symposium PC Chair(2017)&Symposium Chair(2019). He is a senior member of IEEE, IEICE Japan, and a member of IPSJ and ACM.
Presentation(s):
Acceleration of Encryption Algorithms, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic Encryption (FHE)
This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, CRISTALS-Kyber/Dilithium, isogeny based encryption argorithms, and fully homomorphic encryption algorithm.Basics of Asynchronous circuits design
This lecture will overlook basics and variety of asynchronous controlling, from the view point of advantages for low-voltage & variation rich conditions. This lecture takes two extreme example of complete completion detection type asynchronous designs as examples and demonstrate details of operation and performance. In addition, this talk will cover recent trial on design flow of random logic by the self-synchronous circuits.Low-voltage design with autonomous control by gate-level hand-shaking
This lecture will cover basics of asynchronous control including complete completion detection type control, and demonstrate the autonomous gate-level power gating to reduce energy consumption at the energy minimum operating point with asynchronous FPGA as the example. This lecture will also cover low-voltage operations, operation tolerance with power bounce, as well as aging. In addition, this talk will cover recent trial on design flow of random logic by the self-synchronous circuits.
ETH Zürich
Taekwang Jang (S’06-M’13-SM’19) received his B.S. and M.S. in electrical engineering from KAIST, Korea, in 2006 and 2008, respectively. From 2008 to 2013, he worked at Samsung Electronics Company Ltd., Yongin, Korea, focusing on mixed-signal circuit design, including analog and all-digital phase-locked loops for communication systems and mobile processors. In 2017, he received his Ph.D. from the University of Michigan and worked as a post-doctoral research fellow at the same institution. In 2018, he joined ETH Zürich as an assistant professor and is leading the Energy-Efficient Circuits and Intelligent Systems group. He is also a member of the Competence Center for Rehabilitation Engineering and Science, and the chair of the IEEE Solid-State Circuits Society, Switzerland chapter. His research focuses on circuits and systems for highly energy-constrained applications such as wireless sensor nodes and biomedical interfaces. Essential building blocks such as a sensor interface, energy harvester, power converter, communication transceiver, frequency synthesizer, and data converters are his primary interests. He holds 15 patents and has (co)authored more than 80 peer-reviewed conferences and journal articles. He is the recipient of the 2024 IEEE Solid-State Circuits Society New Frontier Award, the SNSF Starting Grant, the IEEE ISSCC 2021 and 2022 Jan Van Vessem Award for Outstanding European Paper, the IEEE ISSCC 2022 Outstanding Forum Speaker Award, and the 2009 IEEE CAS Guillemin-Cauer Best Paper Award. Since 2022, he has been a TPC member of the IEEE International Solid-State Circuits Conference (ISSCC), IMMD Subcommittee, and IEEE Asian Solid-State Circuits Conference (ASSCC), Analog Subcommittee. He also chaired the 2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Frequency Generation Subcommittee. Since 2023, he has been serving as an Associate Editor for the Journal of Solid-State Circuits (JSSC) and was appointed as a Distinguished Lecturer for the Solid-State Circuits Society in 2024.
Presentation(s):
Energy-Efficient Sensor Interface
In the IoT era, a miniaturized sensor system serves as a key leaf node by collecting environment signals and bio-potentials. However, due to the small form factor and limited battery capacity, the energy efficiency of analog and mixed-signal circuits is a critical concern for the long-term operation of the sensor system. Especially, it poses a crucial challenge for the sensor interface circuits whose power consumption needs to be minimized while maintaining acquired signal accuracy and bandwidth. This short course discusses various sensor interface designs with improved noise and power efficiency.Fully integrated DC-DC Conversion
Power management integrated circuits are essential building blocks of consumer electronics for the Internet of Things. Among various architectures, fully integrated power management circuits are promising candidates to provide small form factors and meet the high power density demand of modern computing platforms. However, several characteristics of on-chip passive components limit the performance of the fully integrated DC-DC converters, such as small inductance and Q-factor of the on-chip inductors and large parasitic bottom capacitance or low density of the on-chip capacitors. This short course will introduce the fundamentals of on-chip DC-DC converter designs as well as the latest designs with improved performance.Low Power Frequency Generation
Miniaturization and Interactive communication have been the two main topics dominating recent research on the internet-of-things. The high demand for continuous monitoring of environmental and bio-medical information has accelerated sensor technologies as well as circuit innovations. Simultaneously, the advances in communication methods and the widespread use of cellular and local data links enabled the networking of miniaturized sensor systems. In such systems, the reduction of sleep power is critical to make them sustainable with limited battery capacity or harvested energy. It makes the ultra-low-power wake-up timer a critical building block that must be designed with a stringent power budget. At the same time, precise frequency accuracy is also essential to maintaining synchronization for data communication. This short course will present fundamentals and recent innovations in ultra-low-power frequency reference circuits for miniaturized IoT systems. Two commonly adopted architectures, on-chip RC oscillators, and crystal oscillators, are introduced and discussed in terms of power consumption, noise, temperature sensitivity, line sensitivity, and calibration methods. Finally, a summary of the state-of-the-art designs and related challenges will be introduced.
KAIST, Daejeon, Korea
Hyun-Sik Kim is currently an Associate Professor of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. He received his B.S. degree (Hons.) in electronic engineering from Hanyang University, Seoul, South Korea, in 2009, and his M.S. and Ph.D. degrees in electrical engineering from KAIST, in 2011 and 2014, respectively. His research interests include the CMOS analog-integrated circuit designs, with an emphasis on display drivers, power managements, and sensory readout chips. Prof. Kim was a recipient of two Gold Prizes in the 18th and 19th Samsung Human-Tech Paper Awards in 2012 and 2013, respectively, the IEEE SSCS Pre-Doctoral Achievement Award in 2014, the IEEE SSCS Seoul Chapter Best Student JSSC Paper Award in 2014, and the KAIST Technology Innovation Award in 2022. He served as a guest editor of the IEEE Solid-State Circuits Letters (SSC-L) and is currently serving on the Technical Program Committees (TPC) for the IEEE International Solid-State Circuits Conference (ISSCC), the IEEE Asian Solid-State Circuits Conference (A-SSCC), and the IEEE Custom Integrated Circuits Conference (CICC).
Presentation(s):
Current-Shared Cluster of Multiple Integrated Voltage Regulators (IVRs)
Ganging multiple integrated voltage regulators (IVRs) is crucial for delivering sufficient power in system-on-chip (SoC) applications, particularly those with heavy workloads. However, the utilization of ganged voltage regulators in a shared power-grid is often faces challenges due to supply-current imbalances among the regulators, resulting in larger voltage ripples and thermal hotspots that compromise reliability. The issue is further intensified in inductive-switching IVRs by their tightly spaced on-chip inductors and high switching frequencies, which exacerbate current imbalances.
In this talk, we will explore the state-of-the-art current-sharing techniques for multi-phase IVRs and distributed digital LDOs. We will closely investigate two chip design cases: a 6-phase IVR using bond-wire inductors and a 4-phase IVR with on-chip spiral inductors, focusing on flying-capacitor-based topological solutions for inter-inductor current balancing. Additionally, this talk will include cost-effective solutions to enhance current-sharing accuracy in distributed digital LDO systems without the need for complicated global control mechanisms.
Display Driver ICs – From Basics to Recent Design Challenges
Display driver ICs (DDIs), tasked with digital-to-analog conversion (DAC) and signal drive into pixels, drastically impact image quality in OLED and LED displays. The growing demand for higher visual realism, even in mobile displays, necessitates integrating more source channels into each DDI. Given that the DAC occupies a significant portion of the die area, boosting area efficiency becomes imperative in DDI design to accommodate more channels on a single chip without sacrificing color depth. Moreover, the trend towards high-frame-rate displays (beyond 60Hz) aims to enhance user experience, but faces limitations due to the output buffer’s slew rate in DDIs. Additionally, the emergence of VR/AR micro-displays is introducing new design challenges for CMOS driver and pixel circuits.
This talk will provide a comprehensive investigation of DDI designs, covering foundational principles, technical challenges, and the latest innovations. We will start with an overview of DDIs, assessing their performance across key metrics such as data resolution, die area per channel, linearity, inter-channel deviation, conversion speed, drivability, and power consumption. This talk will then pivot to strategies for balancing some of the performance metrics in DDI design and showcase advanced architectural solutions. It will also cover the progress and hurdles in micro-display drivers, particularly for OLED-on-Silicon and μLED-on-Silicon technologies. In addition, DDIs embedding pixel-current sensing capabilities will be introduced, examining their potential for preemptively addressing burn-in issues.
Exploring Ways to Minimize Dropout Voltage for Energy-Efficient LDO Regulators
Low-dropout (LDO) regulators are ideal off- and on-chip solutions for powering noise-sensitive loads due to their ripple-less output. LDOs also have many benefits over switch-mode dc-dc converters, such as rapid transient response, excellent power supply rejection (PSR), and compact footprint. Unfortunately, they suffer from an inescapable disadvantage: poor power efficiency; this is primarily caused by a considerable dropout voltage (VDO). Reducing VDO to improve efficiency often leads to a significant drop in LDO’s regulation performance. Because of this, most LDOs are designed with a large VDO, making them perceived as energy-consuming components of power management systems.
This talk will delve into effective ways to extremely minimize the dropout voltage without compromising performance, aiming for energy-efficient LDO regulators. We will begin with a thorough investigation of operational principles, analyses, and strategies, exploring trade-offs among key performance metrics. Next, several promising approaches to realizing energy-efficient LDO regulators will be investigated, including traditional digital LDOs, a dual-rail analog/digital-hybrid LDO, a triode-region LDO, and a voltage/current-hybrid (VIH) LDO. Finally, the technical merits and flaws of each high-efficiency LDO topology will be investigated by comparing them. In this talk, I will also share my insights from my experience developing the VIH LDO regulator that achieves 98.6% efficiency and a -75dB PSR at 30kHz.
Boston University
Rabia Yazicigil is an Assistant Professor of ECE Department at Boston University and a Network Faculty at Sabanci University. She was a Postdoctoral Associate at MIT and received her Ph.D. degree from Columbia University in 2016. Her research interests lie at the interface of integrated circuits, bio-sensing, signal processing, security, and wireless communications to innovate system-level solutions for future energy-constrained applications. She has received numerous awards, including the NSF CAREER Award (2024), Early Career Excellence in Research Award for the Boston University College of Engineering (2024), the Catalyst Foundation Award (2021), Boston University ENG Dean Catalyst Award (2021), and “Electrical Engineering Collaborative Research Award” for her Ph.D. research (2016). Dr. Yazicigil is an active member of the Solid-State Circuits Society (SSCS) Women-in-Circuits committee and is a member of the 2015 MIT EECS Rising Stars cohort. She was recently selected as an IEEE SSCS Distinguished Lecturer and elected to the IEEE SSCS AdCom as a Member-at-Large. Lastly, she serves as an Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and on the IEEE ISSCC, RFIC, ESSCIRC, and DAC Technical Program Committees.
Presentation(s):
All-In-One Data Decoders Using GRAND
In 1948, Shannon stated that the best error correction performance comes at longer code lengths. In 1978, Berlekamp, McEliece, and Tilborg established that optimally accurate decoding of linear codes is NP-complete in code length, so there is no optimally accurate universal decoder at long code lengths. Forward error-correction decoding has traditionally been a code-specific endeavor. Since the design of conventional decoders is tightly coupled to the code structure, one needs a distinct implementation for each code. The standard co-design paradigm either leads to significantly increased hardware complexity and silicon area to decode various codes or restrictive code standardization to limit hardware footprint. An innovative recent alternative is noise-centric guessing random additive noise decoding (GRAND). This approach uses modern developments in the analysis of guesswork to create a universal algorithm where the effect of noise is guessed according to statistical knowledge of the noise behavior or through phenomenological observation. Because of the universal nature of GRAND, it allows efficient decoding of a variety of different codes and rates in a single hardware instantiation. The exploration of the use of different codes, including heretofore undecodable ones, e.g., Random Linear Codes (RLCs), is an interesting facet of GRAND. This talk will introduce universal hard-detection and soft-detection decoders using GRAND, which enables low-latency, energy-efficient, secure wireless communications in a manner that is future-proof since it will accommodate any type of code.
This work is joint with Muriel Medard (MIT) and Ken Duffy (Northeastern University).
Cyber-Secure Biological Systems (CSBS)
This talk will introduce Cyber-Secure Biological Systems, leveraging living sensors constructed from engineered biological entities seamlessly integrated with solid-state circuits. This unique synergy harnesses the advantages of biology while incorporating the reliability and communication infrastructure of electronics, offering a unique solution to societal challenges in healthcare and environmental monitoring. In this talk, examples of Cyber-Secure Biological Systems, such as miniaturized ingestible bioelectronic capsules for gastrointestinal tract monitoring and hybrid microfluidic-bioelectronic systems for environmental monitoring, will be presented.Physical-Layer Security for Latency- and Energy-Constrained Integrated Systems
The boom of connected IoT nodes and ubiquity of wireless communications are projected to increase wireless data traffic by several orders of magnitude in the near future. While these future scalable networks support increasing numbers of wireless devices utilizing the EM spectrum, ensuring the security of wireless communications and sensing is also a critical requirement under tight resource constraints. The physical layer has increasingly become the target of attacks by exploiting hardware weaknesses, e.g., side-channel attacks, and signal properties, e.g., time, frequency, and modulation characteristics. This talk introduces common security vulnerabilities within wireless systems such as jamming, eavesdropping, counterfeiting, and spoofing, followed by physical-layer countermeasures, while assessing the trade-offs between performance and security. It examines recent research directions, e.g., secure spatio-temporal modulated arrays, temporal swapping of decomposed constellations, RF fingerprinting, and bit-level frequency hopping, and finally discusses research opportunities looking forward.
Kobe University
Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009. His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, 2.5D and 3D system integration, as well as their applications for hardware security and hardware safety, and cryogenic electronics for quantum computing. Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and served for an Executive Committee Member (2023-present). He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022), the distinguished lecturer (2020-2021, and 2024-present), and currently serves as the chapters vice chair (2022-) of the society. He is an associate editor for IEEE Transactions on VLSI Systems (since 2015).
Presentation(s):
Hardware Security and Safety of IC Chips and Systems
IC chips are key enablers to a smartly networked society and need to be more compliant to security and safety. For example, semiconductor solutions for autonomous vehicles must meet stringent regulations and requirements. While designers develop circuits and systems to meet the performance and functionality of such products, countermeasures are proactively implemented in silicon to protect against harmful disturbances and even intentional adversarial attacks. This talk will start with electromagnetic compatibility (EMC) techniques applied to IC chips for safety to motivate EMC-aware design, analysis, and implementation. It will discuss IC design challenges to achieve the higher levels of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, corroborated with silicon demonstrating analog techniques to protect digital functionality. The EMC and HWS disciplines derived from electromagnetic principles are key to establishing IC design principles for security and safety.IC Chip and Packaging Interactions for Performance Improvements and Security Protections
Interactions of IC chips and packaging structures differentiate the electronic performance among traditional 2D chips and advanced 2.5D and 3D technologies. This presentation starts with their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements as well as full-chip and system level noise simulation. Additionally, the backside of an integrated circuit (IC) chip, more precisely, the backside surface of its Silicon substrate, provides open areas for circuit performance improvements and adversarial security attacks, that are potentially contradictory or traded off in design for performance and security. The talk also explores the security threats over the Si-substrate backside from both passive and active side-channel attack viewpoints and then discusses countermeasure principles.RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance of IC Chips and Systems
Noise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by full-chip and system level simulation. Power and substrate integrity simulation uses chip-package-system board combined models and verifies noise coupling in mixed RF and analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wireless performance through quantitative metrics (e.g. communication throughput and minimum receivable power) among various wireless systems of such as 4G, 5G and GPS. In addition, post-silicon techniques at packaging and assembly stages are potential options to mitigate RF noise coupling problems. The presentation will also include experimental test cases of wireless power transfer modules and unmanned aerial vehicles (drones).Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips
Semiconductor products are potentially compromised for theft, falsification or invalidation by adversarial attempts and even due to unexpected disturbances. This talk provides an overview of physical security threats among semiconductors, and then discusses a broad range of countermeasure techniques. Secure packing exploits vertical structures using post wafer process technologies such as through Si vias, Si backside membranes and Si interposers for proactive prevention from destructive or nondestructive intrusions. Tamper resistance is achieved at the IC level with analog techniques to protect digital functionality. Supply chain security uses hardware Trojan free design verification as well as authentication strategies. Silicon examples will be demonstrated.
University of Ulm
Maurits Ortmanns (Senior Member, IEEE) received the degree of Dr.-Ing. from the University of Freiburg, Germany, in 2004. From 2004 to 2005, he worked at Sci-Worx GmbH, Hannover, Germany, in the area of mixed-signal circuits for biomedical implants. In 2006, he joined the University of Freiburg as an assistant professor. Since 2008, he is a full professor at the University of Ulm, Germany, where he is the director of the Institute of Microelectronics. He is the author of the textbook Continuous-Time Sigma-Delta A/D Conversion, author or co-author of several other book chapters, and over 350 IEEE journal articles and conference papers. He holds many patents. He has served as a program committee member of ISSCC, ESSCIRC, DATE, and ECCTD, as ISSCC EU regional chair, and ISSCC analog subcommittee chair. He has served as an Associate Editor for TCAS, Guest Editor for JSSC, and as a Distinguished Lecturer for SSCS. His research interests include mixed-signal integrated circuit design with special emphasis on data converters and biomedical applications.
Presentation(s):
Efficient High Resolution Incremental ADCs
High-resolution, high-efficiency converters are dominated by noise-shaping and oversampling architectures. However, in applications where true Nyquist-rate conversion is required, such as single-shot conversion, multiplexing, or time-interleaving, neither oversampling nor noise-shaping can be used. This is due to the very concepts that allow them to combine efficiency with performance, introduce memory into the system, and thus prevent sample-to-sample operation. This talk presents approaches to get around this, i.e. to combine Nyquist rate conversion with high power efficiency through innovative architecture and circuit design with a focus on incremental delta-sigma ADCs.Implantable Integrated Circuits and Systems for Neurostimulation and Neuromodulation
Implantable medical devices (IMD) are widely used today to restore function to people with disabilities such as deafness, blindness, heart failure, incontinence, neurological disorders, and many others. Such implantable systems become increasingly challenging when a large number of sensing or stimulating sites need to be realized - space and power budget, safety issues, high bidirectional data rates, as well as the large number of electrical interfaces make the electronic circuit design a complex task of research and development. This talk will highlight some of the recent progress towards the realization of high channel count implantable neural interfaces, covering applications and system examples of neural modulators with high efficiency frontends.
Indian Institute of Technology
Shanthi Pavan received the B.Tech. degree in electronics and communication engineering from IIT Madras, Chennai, India, in 1995, and the M.S. and D.Sc. degrees from Columbia University, New York, NY, USA, in 1997 and 1999, respectively. From 1997 to 2000, he was with Texas Instruments, Warren, NJ, USA, where he worked on high-speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks, Sunnyvale, CA, USA. Since July 2002, he has been with IIT Madras, where he is currently the NT Alexander Institute Chair Professor of Electrical Engineering.Prof.Pavan is the author of Understanding Delta-Sigma Data Converters (second edition, with Richard Schreier and Gabor Temes), which received the Wiley-IEEE Press Professional Book Award for the year 2020. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering, and the Indian National Science Academy, and the recipient of several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award in 2009. He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems—I: Regular Papers and on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC). He has served as a Distinguished Lecturer of the IEEE Circuits and Systems Society and is a two-term Distinguished Lecturer of the Solid-State Circuits Society. He currently serves as the Vice-President of Publications of the IEEE Solid-State Circuits Society and on the editorial board of the IEEE Journal of Solid-State Circuits. He is an IEEE Fellow.
Presentation(s):
Continuous-Time Pipelined Analog-to-Digital Converters - Where Filtering Meets Analog-to-Digital Conversion
If someone told you that the power, noise, distortion, and area of a mixed-signal block could be reduced all at the same time, you'd probably think that this was a lie. It turns out that it is indeed possible sometimes - and this talk will present an example called the continuous-time pipeline (CTP) ADC. The CTP is an emerging technique that combines filtering with analog-to-digital conversion. Like a continuous-time delta-sigma modulator (CTDSM), a CTP has a "nice" input impedance that is easy to drive and has inherent anti-aliasing. However, unlike a CTDSM, a CTP does not require a high-speed feedback loop to be closed. As a result, it can achieve significantly higher bandwidth (like a Nyquist ADC). After discussing the operating principles behind the CTP, we describe the fundamental benefits of the CTP over a conventional signal chain that incorporates an anti-alias filter and a Nyquist-rate converter. We will then show design details and measurement results from a 12-bit ENOB, 100MHz 800MS/s CTP designed in a 65nm CMOS process.Design Challenges in Precision Continuous-Time Delta Sigma Data Conversion
Energy-efficient, high-resolution continuous-time delta-sigma modulators need to overcome several issues that are typically neglected in the design of data converters that target more modest in-band noise spectral densities. Examples of such problems include flicker noise, interconnect resistance and DAC inter-symbol-interference. This talk aims to provide some insight into these issues and describe techniques that can be used to address the formidable challenge of designing such converters. To place things in perspective, the techniques will be discussed in the context of single- and multi-bit CTDSMs that achieve about 105dB SNDR in a 250kHz bandwidth designed in a 180nm CMOS process.
Elmore Family School of Electrical & Computer Engineering, Purdue University
Shreyas Sen is an Elmore Associate Professor of ECE & BME, Purdue University. His current research interests span mixed-signal circuits/systems and electromagnetics for the Internet of Bodies (IoB) and Hardware Security. He has authored/co-authored 3 book chapters, over 200 journal and conference paper and has 25 patents granted/pending. Dr. Sen serves as the Director of the Center for Internet of Bodies (C-IoB) at Purdue. Dr. Sen is the inventor of the Electro-Quasistatic Human Body Communication (EQS-HBC), or Body as a Wire technology, for which, he is the recipient of the MIT Technology Review top-10 Indian Inventor Worldwide under 35 (MIT TR35 India) Award in 2018 and Georgia Tech 40 Under 40 Award in 2022. To commercialize this invention Dr. Sen founded Ixana and serves as the Chairman and CTO and led Ixana to awards such as 2x CES Innovation Award 2024, EE Times Silicon 100, Indiana Startup of the Year Mira Award 2023, among others. His work has been covered by 250+ news releases worldwide, invited appearance on TEDx Indianapolis, NASDAQ live Trade Talks at CES 2023, Indian National Television CNBC TV18 Young Turks Program, NPR subsidiary Lakeshore Public Radio and the CyberWire podcast. Dr. Sen is a recipient of the NSF CAREER Award 2020, AFOSR Young Investigator Award 2016, NSF CISE CRII Award 2017, Intel Outstanding Researcher Award 2020, Google Faculty Research Award 2017, Purdue CoE Early Career Research Award 2021, Intel Labs Quality Award 2012 for industrywide impact on USB-C type, Intel Ph.D. Fellowship 2010, IEEE Microwave Fellowship 2008, GSRC Margarida Jacome Best Research Award 2007, and nine best paper awards including IEEE CICC 2019, 2021 and in IEEE HOST 2017-2020, for four consecutive years. Dr. Sen's work was chosen as one of the top-10 papers in the Hardware Security field (TopPicks 2019). He serves/has served as an Associate Editor for IEEE Solid-State Circuits Letters (SSC-L), Nature Scientific Reports, Frontiers in Electronics, IEEE Design & Test, Executive Committee member of IEEE Central Indiana Section and Technical Program Committee member of TPC member of ISSCC, CICC, DAC, CCS, IMS, DATE, ISLPED, ICCAD, ITC, and VLSI Design. Dr. Sen is a Senior Member of IEEE.
Presentation(s):
Recent Circuit Advances for Resilience to Side-Channel Attacks
Computationally secure cryptographic algorithms, when implemented on physical hardware, leak correlated physical signatures (e.g. power supply current, electromagnetic radiation, acoustic, thermal) which could be utilized to break the crypto engine. Physical-layer countermeasures, guided by understanding of the physical leakage, including circuit-level and layout-level countermeasures promise strong resilience by reducing the physical leakage at the source of the leakage itself. The past decade has seen significant advancements in circuit-level countermeasures, advancing resilience to side-channel attacks. In this talk, we will cover the fundamentals of the leakages and how each countermeasure increases resilience, by diving into the working mechanism of each and comparing the pros and cons of these techniques. The talk concludes by highlighting the open problems and future needs of this field.Secure and Efficient Internet of Bodies using Electro-Quasistatic Human Body Communication
Radiative communication using electromagnetic (EM) fields is the state-of-the-art for connecting wearable and implantable devices enabling prime applications in the fields of connected healthcare, electroceuticals, neuroscience, augmented and virtual reality (AR/VR) and human-computer interaction (HCI), forming a subset of the Internet of Things called the Internet of body (IoB). However, owing to such radiative nature of the traditional wireless communication, EM signals propagate in all directions, inadvertently allowing an eavesdropper to intercept the information. Moreover, since only a fraction of the energy is picked up by the intended device, and the need for high carrier frequency compared to information content, wireless communication tends to suffer from poor energy-efficiency (>nJ/bit). Noting that all IoB devices share a common medium, i.e. the human body, utilizing the conductivity of the human the body allows low-loss transmission, termed as human body communication (HBC) and improves energy-efficiency. Conventional HBC implementations still suffer from significant radiation compromising physical security and efficiency. Our recent work has developed Electro-Quasistatic Human Body Communication (EQS-HBC), a method for localizing signals within the body using low-frequency transmission, thereby making it extremely difficult for a nearby eavesdropper to intercept critical private data, thus producing a covert communication channel, i.e., the human body as a ‘wire’ along with reducing interference.
In this talk, I will explore the fundamentals of radio communication around the human body to lead to the evolution of EQS-HBC and show recent advancements in the field which has a strong promise to become the future of Body Area Network (BAN). I will show the theoretical development of the first Bio-Physical Model of EQS-HBC and how it was leveraged to develop the world’s lowest-energy (<10pJ/b) and world’s first sub-uW Physically and Mathematically Secure IoB Communication SoC, with >100x improvement in energy-efficiency over Bluetooth. Finally, I will highlight the possibilities and applications in the fields of HCI, Medical Device Communication, and Neuroscience including a few videos demonstrations. We will also highlight how such low-power communication in combination with in-sensor intelligence is paving the way forward for Secure and Efficient IoB Sensor Nodes.
Associate Professor, University of Macau
Sai-Weng Sin (Terry) (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical and electronics engineering from the University of Macau, Macao, China, in 2001, 2003, and 2008, respectively. He is currently an Associate Professor in the Faculty of Science and Technology, University of Macau, and is the Deputy Director of State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. He has published 1 book entitled “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters” in Springer, holds 12 patents and over 170 technical journals and conference papers in the field of high-performance data converters and analog mixed-signal integrated circuits. Dr. Sin currently serves as Student Demonstration Program Chair in the Technical Program Committee of the IEEE Asian Solid-State Circuits Conference (A-SSCC), subcommittee chair of the International Conference on Integrated Circuits, Technologies and Applications (ICTA). He served as a Review Committee Member of the International Symposium on Circuits and Systems (ISCAS). He is currently an Associate Editor-in-Chief (Digital Communications) of the IEEE Transaction on Circuits and Systems II – Express Briefs, and also the Associate Editors of IEEE Access and Journal of Semiconductors. He is an IEEE SSCS Distinguished Lecturer for 2024 and 2025. He was the co-recipient of the 2011 ISSCC Silk Road Award, Student Design Contest Award in A-SSCC 2011, and the 2011 State Science and Technology Progress Award (second-class), China.
Presentation(s):
The Historical Development of Data Converters – ADCs that last from 1954 to 2024
Data Converters are one of the key building blocks and the performance bottleneck in the various applications of integrated circuits in our daily lives. The development of data converters is the fundamental driving force behind the modern technology of smart mobile devices based on sensors, communication, and artificial intelligence. However, Data Converters, e.g. SAR ADCs, already have a long history; they served as the key to improving human electronics technology even in the long past, modern, and the foreseeable future. This talk will present the historical development of data converters and review the key data converter development trends in the current era and what we can do.Weightings in Incremental ADCs – How the weights can break and make the Incremental ADCs
Incremental delta-sigma analog-to-digital converters (IADC) are widely used in modern high-fidelity audio, sensors, and IoT low-power applications. Over the past years, the techniques to implement high-resolution IADCs have been significantly improved, for example, in handling the weighting problems inside the IADCs to overcome thermal noise and DAC mismatch issues. This talk offers a comprehensive review of the considerations of weightings in IADCs. The influence of weightings on thermal noise and DAC mismatches are analyzed, and the use of weighting in algorithms is described specifically. The advanced architectures to take advantage of the weightings based on recent academic achievements are presented respectively, with design examples to illustrate the successful practical implementations.
Massachusetts Institute of Technology
Vivienne Sze is an Associate Professor in the Electrical Engineering and Computer Science Department at MIT. She works on computing systems that enable energy-efficient machine learning, computer vision, and video compression/processing for a wide range of applications, including autonomous navigation, digital health, and the internet of things. She is widely recognized for her leading work in these areas and has received awards, including faculty awards from Google, Facebook, and Qualcomm, the Symposium on VLSI Circuits Best Student Paper Award, the IEEE Custom Integrated Circuits Conference Outstanding Invited Paper Award, and the IEEE Micro Top Picks Award. As a member of the Joint Collaborative Team on Video Coding, she received the Primetime Engineering Emmy Award for the development of the High-Efficiency Video Coding video compression standard. She is a co-editor of High Efficiency Video Coding (HEVC): Algorithms and Architectures (Springer, 2014) and co-author of Efficient Processing of Deep Neural Networks (Synthesis Lectures on Computer Architecture, Morgan Claypool, 2020). For more information about Prof. Sze’s research, please visit: http://sze.mit.edu
Presentation(s):
Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
The compute demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed; the increasingly complex algorithms for higher quality of results; and the demands for energy efficiency and real-time performance. In this talk, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption while delivering real-time and robust performance for applications including deep neural networks, data analytics with sparse tensor algebra, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduce the cost of analog-to-digital converters for processing-in-memory accelerators. Throughout the talk, we will highlight important design principles, methodologies, and tools that can facilitate an effective design process.Efficient Computing for Autonomy and Navigation
A broad range of next-generation applications will be enabled by low-energy autonomous vehicles including insect-size flapping wing robots that can help with search and rescue, chip-size satellites that can explore nearby stars, and blimps that can stay in the air for years to provide communication services in remote locations. Autonomy capabilities for these vehicles will be unlocked by building their computers from the ground up, and by co-designing the algorithms and hardware for autonomy and navigation. In this talk, I will present various methods, algorithms, and computing hardware that deliver significant improvements in energy consumption and processing speed for tasks such as visual-inertial navigation, depth estimation, motion planning, mutual-information-based exploration, and deep neural networks for robot perception. We will also discuss the importance of efficient computing to reduce carbon footprint for sustainable large-scale deployment of autonomous vehicles.
Much of the work presented in this talk was developed in the Low-Energy Autonomy and Navigation (LEAN) interdisciplinary group at MIT (http://lean.mit.edu), which is co-directed by Vivienne Sze and Sertac Karaman.
Seoul National University
Jerald Yoo (S’05-M’10-SM’15) received the B.S., M.S., and Ph.D. degrees in Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively. From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Between 2017 and 2024, he was with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, as an Associate Professor. Since 2024, he has been with the Department of Electrical and Computer Engineering, Seoul National University, where he is currently an Associate Professor. He has pioneered research on Body-Area Network (BAN) transceivers for communication/powering and wearable body sensor network using the planar-fashionable circuit board for a continuous health monitoring system. He authored book chapters in Biomedical CMOS ICs (Springer, 2010), Enabling the Internet of Things—From Circuits to Networks (Springer, 2017), The IoT Physical Layer (Chapter 8, Springer, 2019) and Handbook of Biochips (Biphasic Current Stimulator for Retinal Prosthesis, Springer, 2021). His current research interests include low-energy circuit technology for wearable bio-signal sensors, flexible circuit board platform, BAN for communication and powering, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT), and System-on-Chip (SoC) design to system realization for wearable healthcare applications. Dr. Yoo is an IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (2024-2025 and 2017-2018). He also served an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer (2019-2021). He is the recipient or a co-recipient of several awards: IEEE International Solid-State Circuits Conference (ISSCC) 2020 and 2022 Demonstration Session Award (Certificate of Recognition), IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015 and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the founding vice-chair of the IEEE SSCS United Arab Emirates (UAE) Chapter and is the chair of the IEEE SSCS Singapore Chapter. Currently, he serves as an Executive Committee as well as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), ISSCC Student Research Preview (chair), and IEEE Asian Solid-State Circuits Conference (A-SSCC, Emerging Technologies, and Applications Subcommittee Chair), and Steering Committee Member of IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). He is also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society and was an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) and IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS).
Presentation(s):
Body Area Network – Connecting and powering things together around the body
Body Area Network (BAN) is an attractive means for continuous and pervasive health monitoring, providing connectivity and power to the sensors around the human body. Yet its unique and harsh environment gives circuit designers many challenges. As the human body absorbs the majority of RF energy around the GHz band, existing RF radio may not be ideal for communications between and on-body sensors, and so is the RF wireless power transfer. When it comes to energy harvesting, often the harvesting location is not aligned with the sensor location (a.k.a. location mismatch).
To solve the issues, this talk presents the Body Coupled Communication (BCC)-based BAN. BCC BAN utilizes the human body itself as a communication medium, which has orders of magnitude less pathloss when compared to RF in the BAN environment. We will begin with channel characteristics followed by design considerations and transceiver implementation examples. We will then look into what circuit designers should consider in such non-conventional environments. Low energy circuit techniques to overcome their limitations will also be addressed. Lastly, we will discuss the various system aspects of the BAN, including powering up the wearables using the wearable BAN.
Low-power, Low-noise Sensor Interface Circuits for Biomedical Applications
Biomedical and healthcare applications provide attractive opportunities for the semiconductor sector. In both fields, the target is to gather data from multiple sensor nodes with minimal power consumption while maintaining low noise operation. However, designing a sensor interface circuit for such applications is challenging due to its harsh environment. Also, in such cases, the trade-off between available resources and performance among the components both in analog front-end and in the digital back-end is crucial.
This talk will cover the design strategies of sensor interface circuits. Starting from a basic op-amp, we will first explore the difficulties, limitations, and potential pitfalls in sensor interface, and strategy to overcome such issues. Low noise operation leads to two dynamic offset compensation techniques, auto-zeroing, and chopper stabilization. After that, system-level considerations for better key metrics such as energy efficiency will be introduced. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. We will then see how the signal analysis part impacts the analog sensor interface circuit design. The lecture will conclude with interesting aspects and opportunities that lie ahead.
On-Chip Epilepsy Detection: Where Machine Learning Meets Patient-Specific Wearable Healthcare
Epilepsy is a severe and chronic neurological disorder that affects over 65 million people worldwide. Yet current seizure/epilepsy detection and treatment mainly rely on a physician interviewing the subject, which is not effective in infant/children group. Moreover, patient-to-patient and age-to-age variation on seizure pattern make such detection particularly challenging. To expand the beneficiary group to even infants and also to effectively adapt to each patient, a wearable form-factor, the patient-specific system with machine learning is of crucial. However, the wearable environment is challenging for circuit designers due to unstable skin-electrode interface, huge mismatch, and static/dynamic offset.
This lecture will cover the design strategies of patient-specific epilepsy detection System-on-Chip (SoC). We will first explore the difficulties, limitations, and potential pitfalls in wearable interface circuit design and strategies to overcome such issues. Starting from a one op-amp instrumentation amplifier (IA), we will cover various IA circuit topologies and their key metrics to deal with offset compensation. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. Moving on, we will cover the feature extraction and the patient-specific and patient-independent classification using Machine Learning technique. Finally, an on-chip epilepsy detection and recording sensor SoC will be presented, which integrates all the components covered during the lecture. The lecture will conclude with interesting aspects and opportunities that lie ahead.
Towards Monolithic Mobile Ultrasound Imaging System for Medical and Drone Applications
Ultrasound Imaging System (UIS) has been widely used in medical imaging with its non-invasive, non-destructive monitoring nature; but so far the UIS has large form factor, making it difficult to integrate in mobile form factor. For drone and robotic vision and navigation, low-power 3-D depth sensing with robust operations against strong/weak light and various weather conditions is crucial. CMOS image sensor (CIS) and light detection and ranging (LiDAR) can provide high-fidelity imaging. However, CIS lacks depth sensing and has difficulty in low light conditions. LiDAR is expensive with issues of dealing with strong direct interference sources. UIS, on the other hand, is robust in various weather and light conditions and is cost-effective. However, in air channel, it often suffers from long image reconstruction latency and low framerate.
To address these issues, this talk introduces UIS ASICs for medical and drone applications. The medical UIS ASIC is designed to transmit pulse and receive echo through a 36-channel 2-D piezoelectric Micromachined Ultrasound Transducer (pMUT) array. The 36-channel ASIC integrates a transmitter (TX), a receiver (RX), and an analog-to-digital converter (ADC) within the 250- μm pitch channel while consuming low-power and supporting calibration to compensate for the process variation of the pMUT. With its small form factor, Intervascular Ultrasound (IVUS) and Intracardiac Echocardiography (ICE) becomes a viable application. The ASIC in 0.18- μm 1P6M Standard CMOS is verified with both electrical and acoustic experiments with a 6×6 pMUT array. Also, the ASIC for drone applications generates 28 Vpp pulses in standard CMOS and the digital back-end (DBE) achieves 9.83M-FocalPoint/s throughput to effectively translate real-time 3-D image streaming at 24 frames/s. With an 8×8 bulk piezo transducer array, the UIS ASIC is installed on an entry-level consumer drone to demonstrate 7-m range detection while the drone is flying. The talk will conclude with interesting research directions lying ahead in UIS.
SSCS also maintains an Agreement of Cooperation with the IEEE Microwave Theory and Technology Society (MTT-S.) Their list of Distinguished Microwave Lecturers is available here.