Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

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Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

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