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  • David Tadros
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Welcome to Our Five New Members-at-Large for the 2026–2028 Term!

Welcome to Our Five New Members-at-Large for the 2026–2028 Term! 1200 1200 David Tadros

The IEEE Solid-State Circuits Society is happy to welcome and congratulate our newly elected Members-at-Large for the 2026–2028 term. These distinguished individuals will bring valuable expertise and leadership to support the Society’s mission and community.

Our new Members-at-Large are:
– Massimo Alioto
– Chris Mangelsdorf
– Ken Takeuchi
– Kea-Tiong (Samuel) Tang
– Jerald Yoo

We look forward to their contributions in advancing the field of solid-state circuits and strengthening the global SSCS community.

Read more about the election process here 

  • David Tadros
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IEEE SSCS Awards – Now Open for Nominations! Deadline: October 15, 2025

IEEE SSCS Awards – Now Open for Nominations! Deadline: October 15, 2025 940 788 David Tadros
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Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

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Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1882 – 1882
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3550254
Publisher: IEEE

View on IEEE Xplore

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