IEEE Solid-State Circuits Letters – Journals

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A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a $27\mu $ m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 373 – 376
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3636192
Publisher: IEEE

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Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries

Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries 150 150
Author(s): Simon Foster, Scott Block, Daniel McMitchell, Edgar Colin-Beltran, Robert Dailey

Abstract:

A cell monitoring system for performance and safety enhancement is presented. It is the first commercially available single-chip-on-cell near-field contactless solution for automotive battery management, simplifying pack interconnect and reducing points of failure. This letter is a companion paper to the earlier ISSCC paper. It provides further details on the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 369 – 372
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3634340
Publisher: IEEE

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A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN

A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN 150 150
Author(s): Mamoru Sato, Sachio Akebono, Kazuyoshi Yasuoka, Eriko Kato, Masahiro Tsuruta, Chiaki Takano, Kensuke Ota, Kazuki Haraguchi, Masahiro Watanabe, Genki Fujii, Koichiro Yamanaka, Kazunori Yasuda, Satoshi Minami, Katsuhiko Hanzawa, Kohei Matsuda, Akihiko Kato, Yosuke Ueno

Abstract:

This letter presents a CMOS image sensor (CIS) that integrates two operation modes: 1) a high-resolution viewing mode with $0.8~\mu $ m 32 Mpixels and 2) a low-power always-on object recognition mode consuming 2.67 mW at 10 frames/s. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 353 – 356
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628314
Publisher: IEEE

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A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection

A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection 150 150
Author(s): Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria

Abstract:

A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 357 – 360
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628176
Publisher: IEEE

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 365 – 368
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors

A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors 150 150
Author(s): Xiuzhi Zhao, Liheng Liu, Shi Chen, Tianxiang Qu, Qinjing Pan, Dan Li, Gan Guo, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents an ultralow-noise, power-efficient, and pulse-width modulation (PWM)-dimming-tolerant photocurrent readout circuit for under-display ambient light sensor (ALS). A transimpedance amplifier (TIA) with a feedback diode achieves G $\Omega $ -level resistance and 6 fA/ $\surd $ Hz input current noise, enabling sub-pA resolution. Instability and noise folding are mitigated at …

Published in: IEEE Solid-State Circuits Letters
Page(s): 361 – 364
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626378
Publisher: IEEE

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A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology

A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology 150 150
Author(s): Ethan Chou, Hesham Beshary, Nima Baniasadi, Ali M. Niknejad

Abstract:

This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 349 – 352
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626442
Publisher: IEEE

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3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 150 150
Author(s): Xiaosen Liu, Xichen Sun, Renwei Chen, Haozhe Zhang, Zhoutong Liu, Yan Wang

Abstract:

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 341 – 344
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624096
Publisher: IEEE

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An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration 150 150
Author(s): Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim

Abstract:

This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 345 – 348
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624263
Publisher: IEEE

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