In the article [1], Table 2 was incorrectly copied from Table I. The correct Table 2 in [1] is shown below.
This letter presents a 4-element phased-array receiver with code-domain hybrid beamforming (CDHBF) in 65-nm CMOS technology. Code-division multiplexing is used to fully preserve the flexibility in the digital domain while using a single RF interface, which reduces the RF chain complexity, reduces the chip area, and improves power efficiency. Phase …
This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time …
This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple …
This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for …
Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit …
We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc …
We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the …
In this letter, we present an ultrasound (US) imaging system with a low-noise US receiver (RX) and an element-level US transmitter (TX) for a capacitive micromachined ultrasonic transducer (CMUT). The proposed US RX isolates the input parasitic capacitance $(C_{P})$ from the front-end transimpedance stage by using a bandwidth-enhanced current …
