IEEE Journal on Exploratory Solid-State Computational Devices and Circuits – Journals

  • No Comments

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures 150 150
Author(s): Saion K. Roy, Naresh R. Shanbhag

Abstract:

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 22 – 30
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3381888
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories
Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories 150 150
Author(s): Piyush Kumar, Da Eun Shim, Siri Narla, Azad Naeemi

Abstract:

While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 13 – 21
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3357625
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors
Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors 150 150
Author(s): Gautham Rangasamy, Zhongyunshen Zhu, Lars-Erik Wernersson

Abstract:

We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 8 – 12
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3355949
Publisher: IEEE

View on IEEE Xplore

  • No Comments

HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism
HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism 150 150
Author(s): Qianqian Huang, Shaodi Xu, Ru Huang

Abstract:

Field-effect transistors (FETs) switched by quantum band-to-band tunneling (BTBT) mechanism, rather than conventional thermionic emission mechanism, are emerging as an exciting device candidate for future ultralow-power electronics due to their exceptional electronic properties of subthermionic subthreshold swing. However, fundamental limitations in drive current have hindered such technology encountering for high-performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 7
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2023.3338480
Publisher: IEEE

View on IEEE Xplore

Search this website