SSCS “PICO” Open-Source Chipathon

The IEEE Solid-State Circuits Society is pleased to announce its fifth open-source integrated circuit (IC) design contest under the umbrella of its PICO (Platform for IC Design Outreach) program. While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community.

The goal of this year’s event is to foster collaboration and the development of building blocks that will be ported to the open-source GF180MCU PDK across different design areas. Attendees will be organized into teams, each led by IC design experts who will share their knowledge and guide participants through the key steps of the design flow to strengthen our community’s design expertise.

• Creating MOSbius-style chips in GF180MCU
• Digital Building Blocks with an LLM-driven Workflow
• AI/LLM enhanced Analog Automation using gLayout

1. Interested individuals sign up using this form by June 8, 2025.
2. Phase 1 (~June): Participants will explore circuit design and layout in weekly meetings and training sessions. The first weeks will introduce the projects and expectations, leading to team formation by the end of this phase.
3. Phase 2 (~July): Mentors will guide participants on tool installation, design flows for building blocks, and design methodologies with examples to meet circuit specifications.
4. Phase 3 (~August): Design reviews will be scheduled for participants (per team) to present their progress and receive feedback.
5. Phase 4 (~September): All designs will undergo circuit verification and validation with a clean DRC and LVS database by the GF180MCU tape-out deadline.
6. Phase 5 (4 – 5 months after TO): Each team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators.

Each team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators.

The current MOSbius architecture and chip implementation support transistor-level experimentation on breadboards using IC-style circuit topologies. The chip allows learners to bridge the gap between theory and simulation vs. lab measurements before they engage in their own full-custom chip design.

The design of the MOSbius chip itself is very challenging given it combines (analog) transistor cells with an on-chip digitally programmable switch fabric. The verification complexity of highly programmable chips like the MOSbius grows very quickly. The design further needs to be robust against ESD and possible misuse.

Designs can start from the current architecture (using 65nm thick-oxide transistors), but teams are encouraged to explore their own custom transistor-cell designs and switch fabrics. A key requirement is that the chips, besides passive components, should only need minimal external components (e.g., be programmable from a low-cost microcontroller) to build experiments.

A key outcome will be the opportunity to use the fabricated chips to set up labs to train new IC designers across the world. Extra consideration will be given to teams that incorporate exciting experiments using their chip for educational labs.

We propose to design several building blocks – such as small cores, a new set of standard cells and logic families (only library is available here), new memory blocks (like SRAM, eDRAM or other topologies). In parallel, the project will explore developing an LLM-driven digital design flow that can autonomously or semi-autonomously generate complete digital systems from natural language instructions. The goal is to demonstrate how generative AI can speed up digital design workflows, from specification to GDSII, by enabling intelligent interpretation, decision-making, and feedback at every stage. Our long-term vision is to pave the way for scalable, natural language–driven hardware development through a verifiable reward system.

Chipalooza was the first Efabless open-source analog and mixed-signal design challenge event. Its goal was to create a library of different devices that could be reused by other IC designers for education, reference, and enhancement. The IP blocks in the Chipalooza challenge include ADCs, DACs, opamps, filters, temperature sensors, bandgaps, power-on reset, brown-out detector, crystal oscillators, and PLLs.

For the 2025 contest, teams are asked to port one of these IPs from SKY130 to GF180MCU using the GLayout layout automation framework. This framework enables the use of large language models (LLM) to translate natural language instructions into executable commands for the layout process. GLayout was the core of the 2024 SSCS “PICO” open-source chipathon, allowing it to generate DRC and LVS valid layouts for different projects.

The template provided for the Chipathon 2023 will be used to integrate all the designs. Check out this presentation for more details about the template. Also, here is the link to the integrated projects from the 2023 Chipathon.

Reach out to Mehdi Saligane () with any questions.