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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures 150 150
Author(s): Saion K. Roy, Naresh R. Shanbhag

Abstract:

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 22 – 30
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3381888
Publisher: IEEE

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Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories
Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories 150 150
Author(s): Piyush Kumar, Da Eun Shim, Siri Narla, Azad Naeemi

Abstract:

While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 13 – 21
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3357625
Publisher: IEEE

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