Voltage

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A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only …

Published in: IEEE Solid-State Circuits Letters
Page(s): 178 – 181
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

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A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement

A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement 150 150
Author(s): Yahia Ibrahim, Ali M. Niknejad

Abstract:

This work presents a W-band sequential power amplifier (PA) featuring a compact and low-loss output combiner that enhances power back-off (PBO) efficiency by combining a main PA and an auxiliary PA through an isolated combining output network. The proposed architecture is analyzed and experimentally compared to the conventional Doherty PA (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708783
Publisher: IEEE

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An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

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Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

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A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces

A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces 150 150
Author(s): Jun-Cheol Lee, Joo-Hyung Chae

Abstract:

This article presents a transition-driven AC-coupled transceiver (TRX) optimized for low-power and compact die-to-die (D2D) interfaces. To address the limitations of conventional PMOS- and transimpedance-amplifier (TIA)-based receivers (RXs), the proposed RX architecture employs a small 130-fF coupling capacitor to capture only transition information, eliminating the need for bulky …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708634
Publisher: IEEE

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A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces

A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces 150 150
Author(s): Changmin Sim, Seongcheol Kim, Seungwoo Park, Junseob So, Hwaseok Shin, Taehwan Kim, Seon-Been Lee, Minkyun Shim, Chulwoo Kim

Abstract:

This article presents a 27-Gb/s/pin inverter-based delay-matched three-level pulse amplitude modulation (PAM-3) transceiver for short-reach die-to-die (D2D) interfaces. The proposed design uses two parallel, identical offset-programmable transimpedance amplifiers (TIAs) to independently generate two finely tunable PAM-3 reference levels with minimal parasitic loading, enabling multi-level signaling within a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706449
Publisher: IEEE

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A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery 150 150
Author(s): Xuchu Mu, Yang Jiang, Xin Ming, Bo Zhang, Rui P. Martins, Pui-In Mak

Abstract:

This article presents a reconfigurable switched-capacitor (SC) DC–DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702012
Publisher: IEEE

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A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop

A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop 150 150
Author(s): Junyuan Su, Yuxuan Hu, Zherui Zhang, Lei Wang, Yuncai Zhuang, Fei Song, Jiayoon Ru

Abstract:

This article introduces a CP-sampling (CS)-fusion PLL architecture that combines the advantages of PFD-CP PLLs (robust and speedy locking) and sampling PLLs (low jitter/power) in a single loop. The PFD sends pulsewidth-modulation (PWM) pulses to a merged $mathbf {G_{m}}$ /CP (GCP) block so that the phase error …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 20
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704989
Publisher: IEEE

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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