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A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch
A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch 150 150
Author(s): Sheng-Hsi Hung, Tz-Wun Wang, Si-Yi Li, Wei-Chien Hung, Ya-Ting Hsu, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai

Abstract:

This article proposes a gallium nitride (GaN)-based isolated silicon carbide (SiC) MOSFET gate driver with an on-chip metal–insulator–metal (MIM) capacitor that has high data rate and low propagation delay. The improved common-mode transient immunity (CMTI) envelope detection technique eliminates the common-mode current ( $I_{mathrm{CM}})$ to improve …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3386880
Publisher: IEEE

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EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage 150 150
Author(s): Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina

Abstract:

Designing compact and energy-efficient resistive RAM (RRAM) macros is challenging due to: 1) large read/write circuits that decrease storage density; 2) low-conductance cells that increase read latency; and 3) the pronounced effects of routing parasitics on high-conductance cell read energy. Multiple-bits-per-cell RRAM can boost storage density but has further challenges resulting from …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387566
Publisher: IEEE

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Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator
Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator 150 150
Author(s): Peng Xu, Tao Wang, Xueli Zhang, Peng Cao, Jiawei Xu, Zhiliang Hong

Abstract:

This letter analyzes the proposed variable-sawtooth-based PWM controller for the ac-coupled envelope tracking (ET) supply modulator (SM). The ET SM includes a linear amplifier and a switching power modulator (SPM). The SPM maintains the voltage across the ac-coupling capacitor and provides an output current in a power-efficient manner. A 10-MHz …

Published in: IEEE Solid-State Circuits Letters
Page(s): 151 – 154
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3384345
Publisher: IEEE

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A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End
A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End 150 150
Author(s): Hyeyeon Lee, Donguk Seo, Young-Jin Woo, Yoonmyung Lee, Inhee Lee, Youngcheol Chae

Abstract:

This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance $(C_{\mathrm{ IN}})$ into an output current. The resulting current is directly proportional to the ratio of $C_{\mathrm{ IN}}$ to an internal reference capacitor $(C_{\mathrm {REF}})$ and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 135 – 138
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3382813
Publisher: IEEE

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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures 150 150
Author(s): Saion K. Roy, Naresh R. Shanbhag

Abstract:

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 22 – 30
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3381888
Publisher: IEEE

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A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA
A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA 150 150
Author(s): Martin Lee, Motaz Mohamed Elbadry, Kambiz Moez

Abstract:

This article introduces a novel ultra-low-power reference-based low-noise amplifier (LNA) designed to reduce performance variations due to process, voltage, and temperature (PVT) when operating in the subthreshold region. The LNA is embedded within a reference circuit that directly controls the performance of the LNA over PVT variations. By combining the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3375154
Publisher: IEEE

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A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier
A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier 150 150
Author(s): Sheng-Kai Chang, Zhi-Wei Lin, Kuang-Wei Cheng

Abstract:

This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for …

Published in: IEEE Solid-State Circuits Letters
Page(s): 111 – 114
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3375329
Publisher: IEEE

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking 150 150
Author(s): Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1225 – 1234
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3355447
Publisher: IEEE

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