Voltage

  • No Comments

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This paper proposes an offset-canceling discharge-based sensing circuit (OCDC) for STT-MRAM. The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage (VTH) mismatch cancellation, resolving the structural incompatibility between conventional OC schemes and MRL. A diode-connection-based self-biasing mechanism further eliminates the need for an external clamp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Probabilistic Computing with Neuromorphic Elements

Probabilistic Computing with Neuromorphic Elements 150 150
Author(s): Zonglong Li, Laurie E. Calvet

Abstract:

This paper presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130 nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3712198
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode

A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode 150 150
Author(s): Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a high-density (HD) 6T SRAM macro designed in 3-nm FinFET technology with an extended dual-rail (XDR) architecture, addressing active energy and leakage for mobile applications. Two key innovations are introduced: the delayed-wordline in write operation (DEWL) technique and a one-cycle latency low-leakage access mode (1-CLM). The XDR …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1466 – 1476
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3639747
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150
Author(s): Sining Pan, Xiaohan Liu, Ziyi Li, Minge Jiang, Yihang Cheng, Zhong Tang, Huaqiang Wu

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711071
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS 150 150
Author(s): Sangwan Lee, Heedo Jeong, Hanhee Jo, Hwanseok Jung, Jaeduk Han

Abstract:

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713392
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only …

Published in: IEEE Solid-State Circuits Letters
Page(s): 178 – 181
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement

A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement 150 150
Author(s): Yahia Ibrahim, Ali M. Niknejad

Abstract:

This work presents a W-band sequential power amplifier (PA) featuring a compact and low-loss output combiner that enhances power back-off (PBO) efficiency by combining a main PA and an auxiliary PA through an isolated combining output network. The proposed architecture is analyzed and experimentally compared to the conventional Doherty PA (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708783
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

View on IEEE Xplore

Search this website