Voltage

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A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References

A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References 150 150
Author(s): Raghav Bansal, Shouri Chatterjee

Abstract:

This article presents a fully integrated output-capacitor-less (OCL) multi-feedback-loop low-dropout regulator (LDO) with an in-built single bipolar junction transistor (BJT)-based voltage and current reference (VCR) for energy-harvesting Internet of Things (IoT) devices. The proposed architecture comprises four loops, which significantly enhance the DC regulation and transient performance of the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3694415
Publisher: IEEE

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GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection 150 150
Author(s): Mao Li, Sanu K. Mathew, Vivek De, Mingoo Seok

Abstract:

This article presents GUARD, a fully digital, variation-tolerant detector for clock and voltage glitch attacks, featuring an integrated on-demand protection mechanism. Fabricated in 28-nm CMOS, GUARD provides robust security for digital systems by monitoring the system clock for maliciously injected faults. It employs a pair of optimized time-to-digital converters (TDCs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3696209
Publisher: IEEE

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A Zero-Static-Power ADC with Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR from -40 °C to 85 °C

A Zero-Static-Power ADC with Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR from -40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultra-low-power operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only three …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A Third-Harmonic-Enhanced Triple-Push DCO Utilizing Source-Combining Technique

A Third-Harmonic-Enhanced Triple-Push DCO Utilizing Source-Combining Technique 150 150
Author(s): Qiyao Jiang, Zhuo Xu, Quan Pan, Pui-In Mak, Rui P. Martins, Jun Yin

Abstract:

This article presents a detailed investigation into optimizing the amplitude and phase of the transistor’s terminal voltages to generate a high 3rd-harmonic current in the millimeter-wave (mm-Wave) frequency. Based on the analysis, the digitally controlled source-combining triple-push (SCTP) oscillator is derived to significantly enhance the 3rd-harmonic current by introducing …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692500
Publisher: IEEE

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A High-Linearity Shunt-Based In-Line Current Sensor With Self-Heating Compensation and 14.4 V 2 MHz PWM Rejection

A High-Linearity Shunt-Based In-Line Current Sensor With Self-Heating Compensation and 14.4 V 2 MHz PWM Rejection 150 150
Author(s): Heng Ma, Huajun Zhang, Yuyan Liu, Marco Berkhout, Qinwen Fan

Abstract:

This article presents a cost-effective, fully integrated shunt-resistor-based in-line current sensor that delivers high linearity and strong PWM rejection, enabling precise current measurement and control in dynamic driving systems like robotics, imaging, and audio. To mitigate the self-heating of the on-chip shunt resistor, which degrades linearity, a location-based thermal compensation …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3685735
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO

An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO 150 150
Author(s): Feng Bu, Depeng Sun, Dingtao Zeng, Yuan Gao, Bowen Wang, Zhicheng Dong, Xiaoteng Zhao, Hao Xu, Na Yan, Ruixue Ding, Shubin Liu, Zhangming Zhu

Abstract:

This article presents a 13-GHz quadrature charge-pump phase-locked loop (CPPLL) that simultaneously achieves ultra-low jitter and low-spur performance. First, a low-noise resistive-discharge time-amplifying phase-frequency detector (RD-TAPFD) is proposed, achieving extremely low inherent noise and significantly suppressing noise from the following stages. Second, a sampling-based dual-path loop filter effectively suppresses reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3690771
Publisher: IEEE

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A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology

A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 150 150
Author(s): Mu Wu, Yihang Cheng, Xingli Cui, Sining Pan, Huaqiang Wu

Abstract:

This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 109 – 112
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3677301
Publisher: IEEE

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