Transistors

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A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique 150 150
Author(s): Sungjin Kim, Jeonghyun Lee, Yoonse Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon

Abstract:

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 177 – 180
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578546
Publisher: IEEE

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A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS

A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS 150 150
Author(s): Yu-Kai Chen, Yi-Fan Tseng, Wei-Zhe Su, Chun-Hsing Li

Abstract:

A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{mathrm {max }}$ from 239.7 to 367.5 GHz. Furthermore, a $…

Published in: IEEE Solid-State Circuits Letters
Page(s): 165 – 168
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3574413
Publisher: IEEE

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An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K

An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K 150 150
Author(s): Hafeez Raza, Shivendra Singh Parihar, Yogesh Singh Chauhan, Hussam Amrouch, Avinash Lahgere

Abstract:

In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage ( $V_{\min }$ ) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM $V_{\min }$ evaluation, we have measured the FinFETs fabricated using a commercial 5…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 42 – 50
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3560215
Publisher: IEEE

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Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM

Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM 150 150
Author(s): Shivendra Singh Parihar, Shubham Kumar, Swetaki Chatterjee, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 34 – 41
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3547797
Publisher: IEEE

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A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface 150 150
Author(s): Jing Wang, Jun He, Man-Kay Law, Xinzhe Wang, Futian Liang, Lin Cheng

Abstract:

This work proposes a temperature and process-compensated low-power Cryo-CMOS voltage reference without trimming for quantum integrated interface, which is capable of operating continuously from room temperature (RT) down to cryogenic temperatures. By compensating for the main accuracy limiting factors including the process dependence of the transistor threshold voltage, device mismatch …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3242 – 3256
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3530472
Publisher: IEEE

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A Multi-Core Series-Resonance CMOS Oscillator

A Multi-Core Series-Resonance CMOS Oscillator 150 150
Author(s): Shiwei Zhang, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi

Abstract:

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1644 – 1655
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529600
Publisher: IEEE

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A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 150 150
Author(s): Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits

Abstract:

The growing need for approximate matching in data-intensive applications, such as data analytics, machine learning, deep learning, and computational genomics has driven the proposal of our Hamming distance (HD) tolerant content-addressable memory (HD-CAM). HD-CAM features a modified NOR-type associative memory cell that leverages the discharge speed of the matchline (ML) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3009 – 3019
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529715
Publisher: IEEE

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