Transistors

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A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories

A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories 150 150
Author(s): Jianze Wang, Wei Zhang, Xuanyao Fong

Abstract:

The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes, such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 123 – 130
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3616007
Publisher: IEEE

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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS 150 150
Author(s): Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta

Abstract:

This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3612157
Publisher: IEEE

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High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit

High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 150 150
Author(s): Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone

Abstract:

In this letter, we present a high-entropy strong physically unclonable function (PUF) utilizing weak-inversion current mirrors implemented in a standard 65-nm CMOS technology. Each response bit of the proposed PUF relies on the threshold voltage differences of minimum-sized transistors arranged in a $32\times 32$ matrix. The analog operating principle enables encoding …

Published in: IEEE Solid-State Circuits Letters
Page(s): 309 – 312
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3616263
Publisher: IEEE

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A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time 150 150
Author(s): Haris Suhail, Haoran He, Vinod Kurian Jacob, Jiyue Yang, Kang L. Wang, Sudhakar Pamarti

Abstract:

Memory performance has emerged as a critical factor influencing both system speed and energy efficiency. However, conventional memory technologies such as embedded Flash (eFlash) and static RAM (SRAM) encounter significant scalability limitations beyond the 28-nm CMOS node. Among novel emerging memory technologies, spin-transfer-torque magnetic RAM (STT-MRAM) has gained prominence due …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3609342
Publisher: IEEE

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices

Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices 150 150
Author(s): Masanori Natsui, Tomoo Yoshida, Takahiro Hanyu

Abstract:

This article proposes a circuit configuration for an area- and energy-efficient nonvolatile register using magnetic tunnel junction (MTJ) devices, suitable for persistent computation in intermittent computing environments. The proposed configuration, named the reference-load sharing scheme (RLSS), stores 1 bit of information using the resistance of a dedicated MTJ device and a …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 90 – 98
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3611365
Publisher: IEEE

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Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using Margin Propagation

Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using Margin Propagation 150 150
Author(s): Aswin Undavalli, Kareem Rashed, Abdul Rakib Hossain, Gert Cauwenberghs, Shantanu Chakrabartty, Arun Natarajan, Aravind Nagulu

Abstract:

We present a fully analog, multiplier-free, sampled-domain RF correlator to achieve high energy efficiency for radar workloads. The RF correlator employs a split-source follower architecture that leverages the margin propagation (MP) computing paradigm in the sampled domain. As a proof of concept, we implement a $256 \times 256$ fully analog cross correlator …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602920
Publisher: IEEE

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An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm

An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm 150 150
Author(s): Chang Liu, Burak Catli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Xiaochen Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao

Abstract:

This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 281 – 284
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608134
Publisher: IEEE

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A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application

A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application 150 150
Author(s): Sekeon Kim, Giseok Kim, Kyeongrim Baek, Keonhee Cho, Hyunjun Kim, Yeonho Jung, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Abstract:

The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage ( $V_{text {L}}$ ), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3582974
Publisher: IEEE

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