A 3 THz CMOS Image Sensor https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This article presents a 3 THz CMOS image sensor (Tera-CIS). The sensor has a column-parallel readout (CPRO) architecture that integrates an antenna-coupled pixel array and CPRO circuit chains on a monolithic chip. The proposed compact two-transistor (2T) pixel adopts a step-covered patch antenna and a defected ground structure (DGS) to obtain …