Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …