Solids

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An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation

An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation 150 150
Author(s): Yanchao Liu, Kaihang Wang, Yang Li, Xiaohua Yu, Ronghua Ni

Abstract:

This article presents a high-performance 13.2-GHz fractional-N sampling phase-locked loop (PLL). To overcome the nonlinearity bottlenecks inherent in edge-restoring buffers used in conventional digital-to-time converters (DTCs), an intrinsically linear variable-slope sampling phase detector (VS-SPD) is proposed. By seamlessly merging an RC delay network with a sampling phase detector (SPD), the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735859
Publisher: IEEE

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An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory

An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory 150 150
Author(s): Zhengke Yang, Xiao Liu, Haofeng Yu, Zhen Kong, Humiao Li, Liang Ran, Zhichao Lu, Xinhe Feng, Liang Zhao, Yida Li, Jiamin Li, Feichi Zhou, Longyang Lin

Abstract:

Edge vision systems that integrate image sensing and neural-network inference on a single chip are constrained by inter-layer analog-to-digital converters (ADCs) and on-chip weight storage density, which together limit system efficiency and network scale. This article presents a fully analog vision system-on-chip (SoC) with 2-Mbit multi-level-cell (MLC) resistive random access …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737258
Publisher: IEEE

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A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs

A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs 150 150
Author(s): Jianxin Yang, Cheng Huang, Rui P. Martins, Xin Ming, Bo Zhang, Mo Huang

Abstract:

This article presents a modified hybrid Ladder converter for efficient energy recycling in low-duty-cycle systems-on-chip (SoCs) applications. Unlike the conventional schemes that recycle output-capacitor energy back to the battery, the proposed hybrid converter recycles energy into its own capacitors, eliminating battery-recharge losses and improving recycle/recharge efficiency. The design methodology …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738472
Publisher: IEEE

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A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3

A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3 150 150
Author(s): Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz

Abstract:

This article presents a modular 3D stacked manycore processor that integrates a general-purpose RISC-V base die with a domain-specific deep neural network (DNN) accelerator die using a 9 $\mu $ m hybrid-bonded interconnect (HBI). A custom $14 \times 4~\times 2$ 3D network-on-chip (3D NoC) provides a flat, distributed shared-memory address space across 112 tiles, enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735250
Publisher: IEEE

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A 128-Core 340-GHz 2-D Steerable Array With Efficient Third-Harmonic Enhancement Network and 35-dBm Lensless EIRP in 65-nm CMOS

A 128-Core 340-GHz 2-D Steerable Array With Efficient Third-Harmonic Enhancement Network and 35-dBm Lensless EIRP in 65-nm CMOS 150 150
Author(s): Huibo Wu, Xuan Liu, Shunhua Hu, Quanqin Liao, Yuqun Liu, Xingcun Li, Jianhao Gong, Yue Li, Liang Gao, Wenhua Chen

Abstract:

In this article, a coherent 128-core 340-GHz radiator array is presented. In this array, an efficient third-harmonic enhancement network based on the compact multi-coupling transformer balun is proposed. This network boosts the third-harmonic generation by leveraging the mixing effect between the fundamental andsecond-harmonic components, while improving the balance of the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3731143
Publisher: IEEE

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HyFlow: A 28-nm Optical Flow Estimation Accelerator With Redundancy Speculation, Bit-Width-Aware Compression, and Similarity Detection

HyFlow: A 28-nm Optical Flow Estimation Accelerator With Redundancy Speculation, Bit-Width-Aware Compression, and Similarity Detection 150 150
Author(s): Tao Zhang, Yi Zhong, Youming Yang, Jinhao Ruan, Yipeng Gao, Zhaotong Zhang, Yuan Wang

Abstract:

Optical flow estimation with event-based cameras could capture per-pixel motion fields rapidly and efficiently for emerging autonomous intelligence scenarios. To process spike streams from event-based cameras and generate real-valued velocity results, hybrid network architectures integrating spiking neural networks (SNNs) and artificial neural networks (ANNs) have obtained widespread interest. However, when …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3736715
Publisher: IEEE

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A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression

A Multi-Rate SAR-Assisted Exponential-Incremental Pipeline ADC With Noise-Free Passive Residue Transfer and Residue Amplifier Error Suppression 150 150
Author(s): Yuzhou Xiong, Guolong Fu, Xianghui Zhang, Shian Wang, Yuke Shen, Yuhua Liang, Zhong Tang, Yanbo Zhang, Zhangming Zhu

Abstract:

This article presents a multi-rate successive approximation register (SAR)-assisted exponential-incremental (EI) pipeline analog-to-digital converter (ADC) for wireless communication applications. By employing a multi-rate scheme, the ADC harnesses the benefits of oversampling and noise-shaping (NS) techniques while avoiding bandwidth (BW) degradation. To further increase the BW to hundreds of megahertz …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733687
Publisher: IEEE

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A 32-Gb/s/λ, 256-Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3-D-Stacked 7-nm EIC/65-nm PIC Technology

A 32-Gb/s/λ, 256-Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3-D-Stacked 7-nm EIC/65-nm PIC Technology 150 150
Author(s): Sanquan Song, Nikola Nedovic, Nandish Mehta, Angad S. Rekhi, Georgios Kalogerakis, Li Xu, Brian Zimmer, Stephen G. Tell, Yoshinori Nishi, Xi Chen, Ward Lopes, Benjamin G. Lee, Thomas H. Greer, C. Thomas Gray

Abstract:

We present a 32-Gb/s/ $\lambda $ dense wavelength-division multiplexing (DWDM) bandpass-filtered clock-forwarding link with nine channels on a 200-GHz grid: eight for data and one for clock forwarding, intended for next-generation co-packaged optics (CPO). Using an injection-locked oscillation (ILO) technique for jitter filtering, the forwarded clock (FWDCLK) tracks most of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733977
Publisher: IEEE

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A Multi-Channel Thermoelectric Energy Harvesting Interface Realizing Uneven-Input MPPT and 62-mV Start-Up

A Multi-Channel Thermoelectric Energy Harvesting Interface Realizing Uneven-Input MPPT and 62-mV Start-Up 150 150
Author(s): Yunzhe Yang, Mo Huang, Sijun Du

Abstract:

A thermoelectric energy harvesting (TEH) interface for applications using multiple thermoelectric generators (TEGs) is proposed. To improve the maximum power point tracking (MPPT) efficiency under uneven temperature distributions across a large surface, the TEH interface employs a single-inductor multi-channel architecture that individually harvests energy from each TEG. Furthermore, it incorporates …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733544
Publisher: IEEE

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