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A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE

A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE 150 150
Author(s): Yao-Hung Tsai, Ming-Han Chuang, Shen-Iuan Liu

Abstract:

A resistor-less 7-bit source-series-termination (SST) digital-to-analog converter (DAC)-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of the 4:1 multiplexer due to the inter-symbol-interference (ISI), the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 226 – 229
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3722281
Publisher: IEEE

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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 250 – 253
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

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A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems

A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems 150 150
Author(s): Fangming Lou, Haoqiang Deng, Tuo Li, Kai Yuan, Ka Nang Leung, Junmin Jiang, Guoqing Li, Xun Liu

Abstract:

This article proposes a low-dropout regulator (LDO) using a flipped voltage follower (FVF) topology for wide-load-range and low-noise applications. The proposed LDO features a fast load transient response and wide-spectrum power-supply rejection (PSR) performance. To optimize frequency responses at light load and improve PSR performance in the mid-frequency band, an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3739837
Publisher: IEEE

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150
Author(s): DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5409 – 5420
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712021
Publisher: IEEE

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation

A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation 150 150
Author(s): Xuansheng Ji, Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Abstract:

This article presents a coherent polar phase-tracking receiver (PT-RX) for low-power Internet-of-Things(IoT) applications that supports Gaussian frequency-shift keying (GFSK), quadrature amplitude modulation (QAM), and amplitude phase shift keying (APSK). Existing single-path closed-loop receivers achieve low power but suffer from a fundamental tradeoff between loop stability and adjacent channel rejection (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5370 – 5382
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712802
Publisher: IEEE

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Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques

Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques 150 150
Author(s): Ya Zhao, Runchen Wang, Lingao Huang, Haitao Ren, Jun Yin, Pui-In Mak, Li Geng, Chao Fan

Abstract:

This article reports a compact millimeter-wave (mm-wave) quad-core eight-phase oscillator featuring magnetic coupling and dual-injection coupling. Specifically, the quad-core oscillator is integrated in an LC-ring configuration via a windmill-shaping transformer for phase noise (PN) and chip area reduction. The eight-phase oscillator could eliminate the oscillation mode ambiguity and save the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5638 – 5650
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714874
Publisher: IEEE

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A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications

A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications 150 150
Author(s): Xuliang Wang, Renwei Chen, Haoyu Wang, Yang Liu, Wing-Hung Ki, Yan Wang, Xiaosen Liu

Abstract:

This article presents a volumetric integrated voltage regulator (IVR) based on a switched-capacitor-stack-inductor (SCSL) architecture that employs a holistic topology-control-package codesign to overcome the hardware and efficiency bottlenecks of conventional asymmetric multiinductor designs. Based on a discrete-time state-space model, a rigorous root-locus analysis reveals that a rudimentary single voltage-mode control …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5825 – 5837
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713507
Publisher: IEEE

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A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier

A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier 150 150
Author(s): Guo Wei, Rui Zhang, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This article presents a 14-bit 1-GS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) in a 28 nm CMOS process, targeting the optimization of conversion speed and latency. The implemented ADC adopts a two-stage architecture that integrates a residue amplifier (RA) assisted 4-bit/cycle sub-quantizer to tackle the accuracy bottleneck of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738437
Publisher: IEEE

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