SAR-ADC

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An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration 150 150
Author(s): Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim

Abstract:

This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 345 – 348
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624263
Publisher: IEEE

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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS 150 150
Author(s): Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta

Abstract:

This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3612157
Publisher: IEEE

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A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming

A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming 150 150
Author(s): Changde Ding, Yan Zhu, Pengjie Wang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully-digital beamforming in endoscopic and catheter-based 3D-ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20 MS/s SAR ADC. To minimize chip area …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581584
Publisher: IEEE

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