phase-locked loop (PLL)

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A Sampling PLL with Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-in Range

A Sampling PLL with Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-in Range 150 150
Author(s): Hyogyoung An, Changmin An, Sungjin Kim, Heein Yoon

Abstract:

This work presents a sampling PLL (SPLL) that simultaneously achieves sub-sampling PLL-level jitter and wide lock-in range (flock) inherent to SPLL architecture. By employing a high phase detection gain, the proposed SPLL ensures low in-band phase noise dominated by reference, while maintaining robust re-locking without auxiliary frequency-locked loop (FLL). Fabricated …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3710778
Publisher: IEEE

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A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop

A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop 150 150
Author(s): Junyuan Su, Yuxuan Hu, Zherui Zhang, Lei Wang, Yuncai Zhuang, Fei Song, Jiayoon Ru

Abstract:

This article introduces a CP-sampling (CS)-fusion PLL architecture that combines the advantages of PFD-CP PLLs (robust and speedy locking) and sampling PLLs (low jitter/power) in a single loop. The PFD sends pulsewidth-modulation (PWM) pulses to a merged $mathbf {G_{m}}$ /CP (GCP) block so that the phase error …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 20
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704989
Publisher: IEEE

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An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO

An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO 150 150
Author(s): Feng Bu, Depeng Sun, Dingtao Zeng, Yuan Gao, Bowen Wang, Zhicheng Dong, Xiaoteng Zhao, Hao Xu, Na Yan, Ruixue Ding, Shubin Liu, Zhangming Zhu

Abstract:

This article presents a 13-GHz quadrature charge-pump phase-locked loop (CPPLL) that simultaneously achieves ultra-low jitter and low-spur performance. First, a low-noise resistive-discharge time-amplifying phase-frequency detector (RD-TAPFD) is proposed, achieving extremely low inherent noise and significantly suppressing noise from the following stages. Second, a sampling-based dual-path loop filter effectively suppresses reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3690771
Publisher: IEEE

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A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization 150 150
Author(s): Hao Xu, Yizhuo Wang, Ziyang Jiao, Guoyu Li, Yiyun Mao, Shuai Liu, Yan Liu, Jimiao Sang, Qi Guo, Long Kong, Na Yan

Abstract:

A fractional-N digital phase-locked loop employs a novel analog-to-digital converter (ADC)-based phase detector (PD) to achieve direct phase digitization, thereby eliminating the need for a digital-to-time converter (DTC). The high PD gain reduces in-band phase noise, while its high linearity enables all-digital $\Sigma \Delta $ quantization noise cancellation. Implemented with …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671094
Publisher: IEEE

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A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS 150 150
Author(s): Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Abstract:

This article presents a fractional- ${ {N}}$ cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional- ${ {N}}$ reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652928
Publisher: IEEE

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This letter presents a low-jitter digital harmonic-mixing fractional- $N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that …

Published in: IEEE Solid-State Circuits Letters
Page(s): 57 – 60
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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