parasitic capacitance

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Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs 150 150
Author(s): Sadik Yasir Tauki, Rudra Biswas, Rakesh Acharya, Jiahui Duan, Rajiv Joshi, Kai Ni, Vijaykrishnan Narayanan

Abstract:

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 148 – 156
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619908
Publisher: IEEE

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Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions

Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions 150 150
Author(s): Zhendong Li, Yongjuan Shi, Yifan Jiang, Chen Hu, Junting Chen, Mengyuan Hua, Xun Liu, Junmin Jiang

Abstract:

This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias …

Published in: IEEE Solid-State Circuits Letters
Page(s): 277 – 280
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608282
Publisher: IEEE

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A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver

A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver 150 150
Author(s): Yihao Yang, Dan Li, Nan Qi, Binhao Wang

Abstract:

This letter describes an ultra-low-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3584266
Publisher: IEEE

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