Modeling

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Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook

Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook 150 150
Author(s): Patricia Gonzalez-Guerrero, Aaron R. Young, Giuseppe Di Guglielmo, Benjamin Parpillon, Narasinga Rao Miniskar, Nikhil Kumar Cherukuri, Abhay Nayak, Meriam Gay Bautista-Jurney, Mario Vega, George Michelogiannakis, Thom Popovici, Yu Cao, Jeffrey S. Vetter, John Shalf, Farah Fahim

Abstract:

Next-generation scientific instruments in high-energy physics, X-ray imaging, fusion diagnostics, and other data-intensive applications generate data rates that increasingly exceed practical communication bandwidth and power budgets, making the traditional approach of transferring raw data to remote computing systems unsustainable. This paper presents the Vertically Integrated AI for Sensing and High-Performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3742652
Publisher: IEEE

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Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET

Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET 150 150
Author(s): Sufia Shahin, Hafeez Raza, Avinash Lahgere, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

We investigate the impact of cryogenic temperatures on the Single Event Upset (SEU) reliability of the Gate-All-Around (GAA) Nanosheet FET (NSFET) and Complementary FET (CFET) devices. At the device level, we assess heavy-ion radiation (HIR)-induced transients and carrier profiles and compare CFET and NSFET at temperatures from 400K to 77 …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740550
Publisher: IEEE

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A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing

A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing 150 150
Author(s): Zhi Li, Zikang Mei, Wei Tang

Abstract:

In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage ( $V_{th}$ ) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 214 – 222
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736074
Publisher: IEEE

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SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators

SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 205 – 213
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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Physics-Guided Active Learning and Geometry-Aware Electrothermal Screening of Semiconductor Devices: A GaN Case Study

Physics-Guided Active Learning and Geometry-Aware Electrothermal Screening of Semiconductor Devices: A GaN Case Study 150 150
Author(s): Ayoub Sadeghi, Leonid Popryho, Inna Partin-Vaisband

Abstract:

Exploring high-dimensional semiconductor device design spaces under coupled electrothermal constraints remains challenging, particularly in 3-D heterogeneous systems with tightly coupled electrical, thermal, and integration requirements. Conventional TCAD-driven exploration is physically accurate but computationally expensive and offers limited insight into governing parameters. This work presents physics-guided active learning trigate optimization (PALTO), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 231 – 239
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736280
Publisher: IEEE

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DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective

DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective 150 150
Author(s): Yang Xiang, Zhuo Chen, Nicolò Ronchi, Arvind Sharma, Fernando García-Redondo, Subhali Subhechha, Attilio Belmonte, Maarten Rosmeulen, Gouri Sankar Kar, Dwaipayan Biswas, Jan Van Houdt

Abstract:

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3-D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) random-access …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 249 – 255
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740054
Publisher: IEEE

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Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator

Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator 150 150
Author(s): Luqi Zheng, Chang Niu, Shuting Du, Sumi Lee, Amir Massah Bavani, Zehao Lin, Peide D. Ye, Haitong Li

Abstract:

In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 240 – 248
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740041
Publisher: IEEE

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A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications

A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications 150 150
Author(s): Xuliang Wang, Renwei Chen, Haoyu Wang, Yang Liu, Wing-Hung Ki, Yan Wang, Xiaosen Liu

Abstract:

This article presents a volumetric integrated voltage regulator (IVR) based on a switched-capacitor-stack-inductor (SCSL) architecture that employs a holistic topology-control-package codesign to overcome the hardware and efficiency bottlenecks of conventional asymmetric multiinductor designs. Based on a discrete-time state-space model, a rigorous root-locus analysis reveals that a rudimentary single voltage-mode control …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5825 – 5837
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713507
Publisher: IEEE

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150
Author(s): Chaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 199 – 204
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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