Modeling

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Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing

Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing 150 150
Author(s): Sandeep Semwal, Pin Su

Abstract:

The growing demand for energy-efficient computing has intensified interest in highly scalable device technologies such as complementary field-effect transistors (CFETs). In this work, we investigate S-curve engineering for a unique ferroelectric-on-top (FE-o-T) negative-capacitance (NC) CFET through calibrated numerical simulations to assess its potential for ultra-low-power computing and supply-voltage scaling. Our …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740342
Publisher: IEEE

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DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective

DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 150 150
Author(s): Yang Xiang, Zhuo Chen, Nicolò Ronchi, Arvind Sharma, Fernando García-Redondo, Subhali Subhechha, Attilio Belmonte, Maarten Rosmeulen, Gouri Sankar Kar, Dwaipayan Biswas, Jan Van Houdt

Abstract:

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology cooptimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740054
Publisher: IEEE

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QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits

QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits 150 150
Author(s): Mohan Raj Manoharan

Abstract:

Wearable AI workloads such as sensor fusion, physiological inference and uncertainty quantification are probabilistic, yet the neural processing units that serve them are deterministic matrix-multiply engines that discard distributional information at every layer. We describe QEPC, a deferred-evaluation execution model in which probability mass functions are maintained in non-volatile state …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740368
Publisher: IEEE

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A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration

A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration 150 150
Author(s): Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu

Abstract:

Conventional large language models (LLMs) have large parameter sets, making inference costly and energy-intensive; mixture-of-experts (MoEs) mitigates this by activating fewer weights per token, but fine-grained MoE LLMs still face runtime workload variability, inefficient conventional scheduling, and high bandwidth memory (HBM) loading energy/bandwidth demands. A3D-MoE addresses these with 3…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 176 – 184
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3713957
Publisher: IEEE

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150
Author(s): Chaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 199 – 204
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 192 – 198
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators

SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 205 – 213
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing

A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing 150 150
Author(s): Zhi Li, Zikang Mei, Wei Tang

Abstract:

In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage ( $V_{th}$ ) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 214 – 222
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736074
Publisher: IEEE

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A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications

A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications 150 150
Author(s): Xuliang Wang, Renwei Chen, Haoyu Wang, Yang Liu, Wing-Hung Ki, Yan Wang, Xiaosen Liu

Abstract:

This article presents a volumetric integrated voltage regulator (IVR) based on a switched-capacitor-stack-inductor (SCSL) architecture that employs a holistic topology-control-package codesign to overcome the hardware and efficiency bottlenecks of conventional asymmetric multiinductor designs. Based on a discrete-time state-space model, a rigorous root-locus analysis reveals that a rudimentary single voltage-mode control …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5825 – 5837
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713507
Publisher: IEEE

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