Mixers

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4 GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4558 – 4571
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS

An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS 150 150
Author(s): Weiping Wu, Xun Bao, Jingze Wang, Shi Chen, Shulan Chen, Yan Wang, Lei Zhang

Abstract:

This article presents an $H$ -band CMOS receiver chipset that covers a wide frequency range of 228–324 GHz, supporting the entire band of IEEE Std. 802.15.3d. The proposed receiver employs an RF-domain quadrature mixer-first architecture to alleviate the design burden of quadrature local oscillator (LO) signal generation in $H$ -band, which …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4584 – 4599
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3697557
Publisher: IEEE

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A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy

A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy 150 150
Author(s): Maryam Dodangeh, Mark S. Oude Alink, Jan Prummel, Bram Nauta

Abstract:

An ultralow-power Bluetooth low energy (BLE)-compliant crystal-less clock-harvesting receiver is presented that uses the BLE advertising packets (APs) to calibrate an on-chip frequency reference with ±400 ppm initial frequency offset. The proposed front-end, fabricated in 22 nm FDSOI, is capable of pushing the frequency accuracy of the reference further to below ±40/±15 …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718973
Publisher: IEEE

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A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and −56 dBc Spur

A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and −56 dBc Spur 150 150
Author(s): Jaewon Oh, Cheol So, Hyojun Kim, Songcheol Hong, SeongHwan Cho

Abstract:

This article presents a fast-settling 60-GHz local oscillator (LO) for stepped-carrier orthogonal frequency-division multiplexing (OFDM), employing an I/Q-calibrated single-sideband (SSB) mixer with a frequency-tuned injection-locked oscillator (ILO) filter. The SSB mixer enables instantaneous frequency hopping, while the ILO acts as a high- $Q$ bandpass filter that suppresses mixer-induced spurs. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3435 – 3448
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3634591
Publisher: IEEE

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Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation

Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation 150 150
Author(s): Hao Yu, Zhaojing Fu, Lianbo Liu, Qiang Zhou, Taiyun Chi, Sensen Li

Abstract:

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667125
Publisher: IEEE

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A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE

A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE 150 150
Author(s): Yudai Yamazaki, Yohei Morishita, Sunghwan Park, Takaya Uchino, Chenxin Liu, Jun Sakamaki, Akihiro Egami, Ryosuke Hasaba, Ken Takahashi, Tomoki Abe, Tomohiro Murata, Yoichi Nakagawa, Takashi Tomura, Hiroshi Taneda, Kei Murayama, Makoto Tsukahara, Hiroko Ota, Yoko Nakabayashi, Ryuji Kinugawa, Takumi Kojima, Anyi Tian, Kotaro Ito, Chun Wang, Hans Herdian, Yi Zhang, Zheng Li, Wenqian Wang, Hongye Huang, Dingxin Xu, Sena Kato, Michihiro Ide, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Koji Takinami, Kenichi Okada

Abstract:

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1275 – 1293
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665184
Publisher: IEEE

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A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification

A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification 150 150
Author(s): Patrice Abbie D. Legaspi, Shubham Yadav, Mark S. Oude Alink, Bram Nauta

Abstract:

Audio classification in edge devices has many applications and can be implemented at varying levels of complexity, typically consisting of a feature extractor followed by a classifier. Such devices are often always-on, constantly listening to their surroundings, and have a small form factor; therefore, they require low-power operation and high …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655426
Publisher: IEEE

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This letter presents a low-jitter digital harmonic-mixing fractional- $N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that …

Published in: IEEE Solid-State Circuits Letters
Page(s): 57 – 60
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology

A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology 150 150
Author(s): Ethan Chou, Hesham Beshary, Nima Baniasadi, Ali M. Niknejad

Abstract:

This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 349 – 352
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626442
Publisher: IEEE

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