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Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator 150 150
Author(s): Edward Jongyoon Choi, Byeongseon Choi, Jiho Chun, Minkyu Je, Bongjin Kim

Abstract:

Formal robustness verification of neural networks is essential for deploying machine learning (ML) systems in safety-critical applications. However, existing verification frameworks are predominantly software-based, incurring prohibitive computational costs and long runtimes, severely limiting scalability and practical deployment. Although symbolic interval analysis enables scalable over-approximate verification, its effectiveness is limited by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3707324
Publisher: IEEE

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A Nonvolatile AI-Edge Processor With Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro Using Dynamic Floating-/Fixed-Point Accumulation

A Nonvolatile AI-Edge Processor With Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro Using Dynamic Floating-/Fixed-Point Accumulation 150 150
Author(s): De-Qi You, Win-San Khwa, Bo Zhang, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

Abstract:

Nonvolatile AI-edge processors based on near-memory-compute (nvNMC) enable energy-efficient multiply-and-accumulate (MAC) operations with short wakeup latency for edge inference operations. Lossless compression is required for floating-point (FP) neural network (NN) models under on-chip memory capacity constraints; however, this imposes several challenges: 1) data decompression overhead due to lossless FP weight encoding; 2) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3705432
Publisher: IEEE

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A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits

A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits 150 150
Author(s): Ming-Che Li, Archisman Ghosh, Risi Kumar Jaiswal, Supriyo Datta, Shreyas Sen

Abstract:

Qubit-based quantum annealing processors operate at ultra-low temperatures (15 mK) requiring enormous cooling energy. Consequently, there is a lot of interest in quantum Monte Carlo (QMC) algorithms that can be used to emulate quantum computing on classical machines. However, prior classical emulators implemented on CPUs, GPUs, or field-programmable gate arrays (FPGAs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699984
Publisher: IEEE

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A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation

A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation 150 150
Author(s): Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Adiwena Putra, Jaehoon Heo, Joo-Young Kim

Abstract:

Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3689546
Publisher: IEEE

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QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC

QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC 150 150
Author(s): Minkyung Kim, Hyeongseok Seo, Songhyeon Kim, Jung-Hoon Chun, Seong-Jin Kim, Jaehyuk Choi

Abstract:

This article presents a high-resolution (HR) CMOS light detection and ranging (LiDAR) sensor capable of generating quarter video graphics array (QVGA) ( $320~{\times }~240$ ) depth images. To support high pixel density, the sensor employs a compact 6-transistor (6-T) nMOS-only single-photon avalanche diode (SPAD) analog front-end (AFE) with a column-shared active recharge circuit. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687569
Publisher: IEEE

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