Memory

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HyFlow: A 28-nm Optical Flow Estimation Accelerator With Redundancy Speculation, Bit-Width-Aware Compression, and Similarity Detection

HyFlow: A 28-nm Optical Flow Estimation Accelerator With Redundancy Speculation, Bit-Width-Aware Compression, and Similarity Detection 150 150
Author(s): Tao Zhang, Yi Zhong, Youming Yang, Jinhao Ruan, Yipeng Gao, Zhaotong Zhang, Yuan Wang

Abstract:

Optical flow estimation with event-based cameras could capture per-pixel motion fields rapidly and efficiently for emerging autonomous intelligence scenarios. To process spike streams from event-based cameras and generate real-valued velocity results, hybrid network architectures integrating spiking neural networks (SNNs) and artificial neural networks (ANNs) have obtained widespread interest. However, when …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3736715
Publisher: IEEE

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3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems

3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems 150 150
Author(s): Arya Upadhyay

Abstract:

Moving sensor data and neural-network operands through conventional external-memory hierarchies can constitute a substantial fraction of the energy required for edge inference. Motivated by a three-tier near-sensor organization, this work evaluates memory localization using a controlled architecture-level study and an independent transistor-level communication-link analysis. Five convolution configurations are evaluated on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3735890
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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A 28-nm, 8.3-mm2, 76.9-μJ/Pairing Compiler-Driven Crypto-Processor for Hybrid ZKP–PBC Application With Software–Hardware Co-Design

A 28-nm, 8.3-mm2, 76.9-μJ/Pairing Compiler-Driven Crypto-Processor for Hybrid ZKP–PBC Application With Software–Hardware Co-Design 150 150
Author(s): Xiangren Chen, Bohan Yang, Jinfan Zhang, Yifan Jiang, Wenping Zhu, Hanning Wang, Min Zhu, Aoyang Zhang, Leibo Liu

Abstract:

Zero-knowledge proof (ZKP), one of the most popular privacy-preserving schemes, enables the prover to convince the verifier of a certain statement’s correctness without leaking any private information. Among them, the Pairing-based succinct non-interactive argument of knowledge (zkSNARK), like Groth16 and Plonk, featuring succinct proof size and constant-time verification, is …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3722561
Publisher: IEEE

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miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator 150 150
Author(s): Krishna Sai Tarun Ramapragada, Utsav Banerjee

Abstract:

We present the first ASIC demonstration of SQIsign, an isogeny-based National Institute of Standards and Technology (NIST)-candidate post-quantum digital signature scheme. Our optimized Montgomery modular multiplier circuit design enables $2\times $ speedup and energy savings, while an efficient memory organization provides a 31% area savings. We implement SQIsign-1D-Uncompressed signature verification …

Published in: IEEE Solid-State Circuits Letters
Page(s): 238 – 241
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720807
Publisher: IEEE

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CTH-CAM: A Cryogenic eDRAM-Based CAM With 1–26 Tunable Hamming Distance

CTH-CAM: A Cryogenic eDRAM-Based CAM With 1–26 Tunable Hamming Distance 150 150
Author(s): Jincheng Wang, Yuxin Zhou, Bin Ning, Lintao Lan, Yifei Li, Xufeng Kou, Yuhao Shu, Yajun Ha

Abstract:

Cryogenic approximate content-addressable memory (ACAM) offers an appealing solution that allows mismatches between the query and the stored data, measured by the Hamming distance (HD). However, in ACAM designs, increasing the word length shrinks the matchline (ML) voltage spacing between adjacent HD tolerance levels, thereby limiting the tunable-HD tolerance range …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3722705
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3193 – 3207
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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MTDiff: A Multi-Task Diffusion Accelerator With Bandwidth-Aware Memory Partition and Efficient Digital Compute-in-Memory

MTDiff: A Multi-Task Diffusion Accelerator With Bandwidth-Aware Memory Partition and Efficient Digital Compute-in-Memory 150 150
Author(s): Jiaqi Zhou, Yiqi Jing, Yiyang Sun, Siyuan He, Le Ye, Tianyu Jia

Abstract:

Initially applied to image synthesis, diffusion models have rapidly expanded into various content generation tasks, such as 3-D scene reconstruction and video generation, due to the superior generative quality. Based on our observations, the imbalanced operational intensities across diffusion model layers lead to suboptimal hardware utilization due to inadequate bandwidth …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718715
Publisher: IEEE

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FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing

FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing 150 150
Author(s): Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang

Abstract:

This article introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction (FE) and on-device few-shot learning (FSL). The accelerator addresses fundamental challenges of on-device learning (ODL) for resource-constrained edge applications through two synergistic modules: a parameter-efficient feature extractor (FE) employing weight clustering and an FSL classifier …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709217
Publisher: IEEE

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