linearity

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A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique

A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique 150 150
Author(s): Linran Zhao, Yiming Han, Yaoyao Jia

Abstract:

This article presents a low-power continuous-time (CT) $G_{mathrm {M}}$ -C-based $Delta Sigma $ analog-to-digital converter (ADC) employing capacitive input feedforward and a duty-cycled $G_{mathrm {M}}$ technique to enhance linearity while maintaining high energy efficiency. The ADC employs a CT capacitive network for concurrent signal summation and quantization, enabling input …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733305
Publisher: IEEE

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A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification 150 150
Author(s): Hongjiang Chen, Jingxiang Wang, Kaize Zhang, Shizhan Mo, Liang Qi, Chao Zhao, Hao Zhang, Zhang Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730470
Publisher: IEEE

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A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz

A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz 150 150
Author(s): Heng Ma, Huajun Zhang, Yuyan Liu, Qinwen Fan

Abstract:

This article presents a fully integrated shunt-resistor-based in-line current sensor for high-voltage (HV) pulse-width modulation (PWM)-based power systems. Floating-Gm current sensors are effective at rejecting HV PWM common-mode (CM) interference, but their linearity degrades at high CM voltages due to the substrate current-induced body effect (SCBE) in HV laterally …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3716767
Publisher: IEEE

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A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer

A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer 150 150
Author(s): Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This work presents a pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a current-buffer-based integrating sampler that combines an easy-to-drive resistive input with high linearity. To overcome the linearity and swing limitations of conventional current-integrating samplers (CISs), the frontend employs a $G_{m}$ -boosted continuous-time (CT) floating charge transferrer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714848
Publisher: IEEE

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A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

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A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications

A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications 150 150
Author(s): Xichen Li, Ahmed Refaat Aboulsaad, Elpida Karapepera, Yi-Hsiang Huang, Po-Hao Cheng, Charles Chien, Jacques Christophe Rudell

Abstract:

Future full-duplex (FD) radio systems require highly tunable self-interference (SI) cancellers with rapid adaptation to mitigate dynamic SI profiles in wireless environments. This article presents a 2.4-GHz RF SI canceller chip with extensive tuning capabilities that operates with a machine-learning (ML)-augmented adaptation loop for FD transceivers. The proposed design …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715631
Publisher: IEEE

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A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS 150 150
Author(s): Sangwan Lee, Heedo Jeong, Hanhee Jo, Hwanseok Jung, Jaeduk Han

Abstract:

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713392
Publisher: IEEE

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A High-Linearity Shunt-Based In-Line Current Sensor With Self-Heating Compensation and 14.4 V 2 MHz PWM Rejection

A High-Linearity Shunt-Based In-Line Current Sensor With Self-Heating Compensation and 14.4 V 2 MHz PWM Rejection 150 150
Author(s): Heng Ma, Huajun Zhang, Yuyan Liu, Marco Berkhout, Qinwen Fan

Abstract:

This article presents a cost-effective, fully integrated shunt-resistor-based in-line current sensor that delivers high linearity and strong PWM rejection, enabling precise current measurement and control in dynamic driving systems like robotics, imaging, and audio. To mitigate the self-heating of the on-chip shunt resistor, which degrades linearity, a location-based thermal compensation …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3685735
Publisher: IEEE

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A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC

A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC 150 150
Author(s): Kaiwen Zhou, Jianhong Zhou, Yijie Li, Yuying Li, Tian Dong, Zhiliang Hong, Jiawei Xu

Abstract:

A high-precision, direct-digitization sensor readout (DD-RO) based on a continuous-time delta-sigma modulator (CT- $\Delta \Sigma $ M) is presented. The proposed DD-RO incorporates several key innovations to enhance performance. First, a pseudo-differential current-balancing integrator (PD-CBI) significantly extends the linear input range, whereas its intrinsically limited common-mode input range and CMRR are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686843
Publisher: IEEE

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