linearity

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A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, C. Patrick Yue

Abstract:

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 273 – 276
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3603569
Publisher: IEEE

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MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication

MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Laith Shamieh, Narasimha Vasishta Kidambi, Isha Chakraborty, Saibal Mukhopadhyay

Abstract:

A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 213 – 216
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3590757
Publisher: IEEE

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A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression 150 150
Author(s): Jamie C. Ye, Alain H. Antón, Sanaz Sadeghi, Russ H. Huang, Alyosha C. Molnar

Abstract:

A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1541 – 1553
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3546082
Publisher: IEEE

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Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 150 150
Author(s): Jianzi Jin, Shifan Gao, Cimang Lu, Xiang Qiu, Yi Zhao

Abstract:

A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 19 – 24
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3539470
Publisher: IEEE

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A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation

A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation 150 150
Author(s): Rundi Wu, Yetong Wang, Ran Hong, Zongle Ma, Kenan Xie, Fanyi Meng, Kaixue Ma, Keping Wang

Abstract:

This article presents a mixer-first blocker-tolerant receiver (RX) with effective switch resistance ( ${R} _{\text {SW}}$ ) compensation and high-Q selectivity. By analyzing the impact of non-ideal 1/N LO duty cycle and effective ${R} _{\text {SW}}$ on mixer-first RX, an effective ${R} _{\text {SW}}$ compensation technique is proposed to mitigate noise figure (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1554 – 1569
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529681
Publisher: IEEE

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A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback

A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback 150 150
Author(s): Stef van Zanten, Ronan A. R. van der Zee, Bram Nauta

Abstract:

This article presents a capacitive stacking mixer-first receiver (MF-RX) with a higher order capacitive feedback (CFB) loop designed to increase interferer rejection right at the mixer baseband (BB) node, benefiting both the out-of-band (OOB) linearity of the passive mixer switches and the active BB circuitry. The CFB loop consists of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3148 – 3163
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3524278
Publisher: IEEE

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