Joining processes

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 50-Gb/s Baud-Rate Burst-Mode Receiver Using a Phase Uncertainty Reduction Scheme Achieving 8-ns Phase Locking for 50G-PON in 28-nm CMOS

A 50-Gb/s Baud-Rate Burst-Mode Receiver Using a Phase Uncertainty Reduction Scheme Achieving 8-ns Phase Locking for 50G-PON in 28-nm CMOS 150 150
Author(s): Pingyi Cai, Xiongshi Luo, Ruixian Zhang, Kun Zhang, Wenhan Guan, Jiayao Li, Wenkang Luo, Yangyi Zhang, Quan Pan

Abstract:

This article presents a 50-Gb/s baud-rate burst-mode receiver (BMRX) for 50G-PON. A phase uncertainty reduction (PUR) scheme is proposed to narrow the maximum phase search range from 1 unit interval (UI) to 0.5 UI, thereby reducing the phase locking overhead while preserving low power consumption. To maintain robust burst acquisition across …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3728469
Publisher: IEEE

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A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends

A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends 150 150
Author(s): S. Sarah Feng, Fuzhan Chen, H. Bruce Bao, R. Matthew Ma, Kangping Zhong, P. T. Alan Lau, C. Patrick Yue

Abstract:

This letter presents a broadband, high-optical modulation amplitude (OMA) GaN-based 1-to-N VCSEL driver implemented in a 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 242 – 245
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720689
Publisher: IEEE

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Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback

Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback 150 150
Author(s): Luke D. Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn

Abstract:

Boolean satisfiability (SAT or $k$ -SAT, $k ge 3$ ) is a binary combinatorial optimization problem (COP) that is challenging for traditional classical computing to address in polynomial time. Quantum and quantum-inspired systems have been touted to tackle these and similar nondeterministic polynomial-time (NP) problems. This work describes Medusa, a quantum-inspired $k$ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726445
Publisher: IEEE

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An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS

An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS 150 150
Author(s): Weiping Wu, Xun Bao, Jingze Wang, Shi Chen, Shulan Chen, Yan Wang, Lei Zhang

Abstract:

This article presents an $H$ -band CMOS receiver chipset that covers a wide frequency range of 228–324 GHz, supporting the entire band of IEEE Std. 802.15.3d. The proposed receiver employs an RF-domain quadrature mixer-first architecture to alleviate the design burden of quadrature local oscillator (LO) signal generation in $H$ -band, which …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4584 – 4599
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3697557
Publisher: IEEE

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A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS

A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS 150 150
Author(s): Hsiang-Chun Cheng, Mayank Palaria, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen

Abstract:

This letter presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 222 – 225
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717659
Publisher: IEEE

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Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 210 – 213
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

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A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation

A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation 150 150
Author(s): Ahmet Yusuf Salim, Soner Seçkiner, Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse

Abstract:

Recent years have seen growing interest in custom and nature-inspired computing methods for solving computationally challenging combinatorial optimization problems. The Boolean satisfiability (SAT), a canonical nondeterministic polynomial (NP)-complete problem, has remained a focal point due to its wide applicability in artificial intelligence, cryptography, and formal verification. This article presents …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721413
Publisher: IEEE

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Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 135 – 143
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704358
Publisher: IEEE

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