Integrated circuits

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Benchmarking of Emerging Material-Based TCAMs

Benchmarking of Emerging Material-Based TCAMs 150 150
Author(s): Ashwin Tunga, Junzhe Kang, Zijing Zhao, Ankit Shukla, Wenjuan Zhu, Shaloo Rakheja

Abstract:

This work presents a comprehensive benchmarking of ternary content-addressable memory (TCAM) implementations using timing-accurate SPICE simulations, systematically comparing conventional CMOS designs with emerging device technologies, including magnetic tunnel junctions (MTJs), ferroelectric tunnel junctions (FTJs), ferroelectric field-effect transistors (FeFETs), and 2-D reconfigurable field-effect transistors (2D RFETs). Key performance metrics, including search …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 104 – 112
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3687143
Publisher: IEEE

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A Capacitor-Free Hybrid-Process Low Dropout Regulator With Ultrahigh-Gain Amplifier and Super Source Follower for 0.297 mV/A Load Regulation and 0.024 mV/V Line Regulation

A Capacitor-Free Hybrid-Process Low Dropout Regulator With Ultrahigh-Gain Amplifier and Super Source Follower for 0.297 mV/A Load Regulation and 0.024 mV/V Line Regulation 150 150
Author(s): Yu-Ting Huang, Xiao-Quan Wu, Chi-Yu Chen, Po-Jui Chiu, Chien-Wei Cho, Tz-Wun Wang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Sheng-Hsi Hung, Chih-Fang Huang, Philex Ming-Yan Fan, Tsorng-Juu Liang, Hann-Huei Tsai

Abstract:

The proposed capacitor-free hybrid-process low-dropout regulator (LDO) achieves 900-mA maximum current capacity and 99.99% peak current efficiency with 90 $\mu $ A quiescent current. By combining GaN and silicon processes, the proposed Ultrahigh gain amplifier (UHGA) enables a high loop gain to achieve 0.297-mV/A load regulation and 0.024-mV/V line regulation. Furthermore, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702962
Publisher: IEEE

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A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy

A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy 150 150
Author(s): Seonghyun Park, Song-I Cheon, Haidam Choi, Sein Oh, Sohmyung Ha, Minkyu Je

Abstract:

This article presents an electrical bio-impedance (bioZ) spectroscopy integrated circuit (IC) that achieves both high-throughput and high-accuracy. The proposed phase-locked sampling (PLS) scheme, which employs a sampling phase-locked loop (SPLL) and a reference resistor ( $R_{\textit {REF}}$ ), enables fast and precise impedance demodulation. By extracting the impedance components through sampling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704052
Publisher: IEEE

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The Impact of Magnetic Field on Defective FDSOI and FinFET Devices

The Impact of Magnetic Field on Defective FDSOI and FinFET Devices 150 150
Author(s): Munazza Sayed, Hussam Amrouch

Abstract:

This article explores the efficacy of a unique defect detection mechanism for the FinFET and FDSOI transistors: magnetomodulation of drain current. Using multiphysics technology CAD (TCAD), we model the impact of static and transient magnetic fields on drain current in the following defect-free and defective devices: 1) FDSOI with interface trap …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 113 – 119
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3686904
Publisher: IEEE

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A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits

A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits 150 150
Author(s): Ming-Che Li, Archisman Ghosh, Risi Kumar Jaiswal, Supriyo Datta, Shreyas Sen

Abstract:

Qubit-based quantum annealing processors operate at ultra-low temperatures (15 mK) requiring enormous cooling energy. Consequently, there is a lot of interest in quantum Monte Carlo (QMC) algorithms that can be used to emulate quantum computing on classical machines. However, prior classical emulators implemented on CPUs, GPUs, or field-programmable gate arrays (FPGAs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699984
Publisher: IEEE

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OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication

OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication 150 150
Author(s): Shady Agwa, Yihan Pan, Georgios Papandroulidakis, Themis Prodromakis

Abstract:

Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 56 – 64
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3680281
Publisher: IEEE

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A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges

A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges 150 150
Author(s): Shin Han, Gicheol Shin, Jongmin Lee, Yoonmyung Lee

Abstract:

A complementary positive feedback-assisted current mirror-based level shifter (CPFLS) is proposed to reliably convert subthreshold signals to higher voltages. By adopting a positive feedback structure, the CPFLS mitigates the delay degradation and short-circuit current issues inherent in a prior art, WCMLS, due to its negative feedback design. Additionally, the CPFLS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687258
Publisher: IEEE

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A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC

A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC 150 150
Author(s): Kaiwen Zhou, Jianhong Zhou, Yijie Li, Yuying Li, Tian Dong, Zhiliang Hong, Jiawei Xu

Abstract:

A high-precision, direct-digitization sensor readout (DD-RO) based on a continuous-time delta-sigma modulator (CT- $\Delta \Sigma $ M) is presented. The proposed DD-RO incorporates several key innovations to enhance performance. First, a pseudo-differential current-balancing integrator (PD-CBI) significantly extends the linear input range, whereas its intrinsically limited common-mode input range and CMRR are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686843
Publisher: IEEE

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HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro

HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro 150 150
Author(s): Gaurav Kumar K, Yatharth Agarwal, Kaushik Roy

Abstract:

This letter presents HyFPCiM, a 65-nm FP8 compute-in-memory (CiM) macro that enables sub-mW floating-point (FP) inference using error-sensitivity-aware FP partitioning (EAP). EAP maps exponent processing to a digital CiM (DCiM) path and mantissa accumulation to an analog CiM (ACiM), avoiding the power- and area-intensive adder-tree-based accumulation used in prior FP-CiM …

Published in: IEEE Solid-State Circuits Letters
Page(s): 146 – 149
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3688988
Publisher: IEEE

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