in-memory computing (IMC)

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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures 150 150
Author(s): Saion K. Roy, Naresh R. Shanbhag

Abstract:

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 22 – 30
Year of Publication: 2024
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2024.3381888
Publisher: IEEE

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3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design
3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design 150 150
Author(s): Gopikrishnan R. Nair, Pragnya S. Nalla, Gokul Krishnan, Anupreetham, Jonghyun Oh, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Mingoo Seok, Jae-Sun Seo, Yu Cao

Abstract:

Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit …

Published in: IEEE Solid-State Circuits Letters
Page(s): 119 – 122
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3375110
Publisher: IEEE

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