impedance

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A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification 150 150
Author(s): Jeroen Ponte, Roel Plompen, Emiel Zijlma, Eric A. M. Klumperink, Harijot Singh Bindra, Bram Nauta

Abstract:

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611114
Publisher: IEEE

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A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS

A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS 150 150
Author(s): Yongjae Park, Yeong-Jin Mo, Jeong-Hoon Kim, Gert Cauwenberghs, Seong-Jin Kim

Abstract:

This article presents a biopotential recording analog front-end (AFE) specifically tailored for a two-electrode measurement system, capable of capturing small biopotential signals while tolerating a large common-mode interference (CMI) over 130 VPP. By leveraging the Miller effect, the proposed CMI-Follower provides a significantly low common-mode input impedance ( $Z_{\text {IN-CM-C}}$ ), achieving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613410
Publisher: IEEE

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A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC

A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC 150 150
Author(s): Mietek Dabrowski, Filip Tavernier, Paul Leroux

Abstract:

This article presents the design of a four-channel front-end application specific integrated circuit (ASIC), ATLAS liquid argon front-end (ALFE), developed for the readout of the liquid-argon calorimeter (LAr) detector in the ATLAS experiment at the Large Hadron Collider (LHC). ALFE enables the readout of current signals induced in the LAr …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602751
Publisher: IEEE

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS

A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS 150 150
Author(s): Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua

Abstract:

This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an …

Published in: IEEE Solid-State Circuits Letters
Page(s): 217 – 220
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3591570
Publisher: IEEE

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A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects

A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects 150 150
Author(s): Wei-Yu Lin, Jun-Chau Chien

Abstract:

Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an …

Published in: IEEE Solid-State Circuits Letters
Page(s): 181 – 184
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578942
Publisher: IEEE

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A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range

A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range 150 150
Author(s): Jiahao Wang, Shen Ye, Shiqi Zhang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8- $mu $ V input offset (10 samples) and 33.5- $mu $ V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 173 – 176
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3576393
Publisher: IEEE

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A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150
Author(s): Junhui Gu, John Ma, Azhar Ahmed Chowdhury, Jianmin Guo, Xin Zhang, Jackson Ding, Hui Wang, Ken Chang

Abstract:

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1289 – 1298
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545483
Publisher: IEEE

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A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression 150 150
Author(s): Jamie C. Ye, Alain H. Antón, Sanaz Sadeghi, Russ H. Huang, Alyosha C. Molnar

Abstract:

A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1541 – 1553
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3546082
Publisher: IEEE

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