impedance

A Pseudo-Series Resonance CMOS Oscillator

A Pseudo-Series Resonance CMOS Oscillator 150 150

Abstract:

This article presents a single-core, low-phase-noise (PN) digitally controlled oscillator (DCO) employing a pseudo-series resonance (pseudo-SR) technique with a transformer-based resonator. The proposed pseudo-SR resonator offers two key advantages: 1) a low impedance with a 180° phase shift at the impedance pole, emulating series resonance (SR) to enable single-stage oscillation and reduce …

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A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications

A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications 150 150

Abstract:

This article presents a reconfigurable dual-path dual-band low noise amplifier (LNA) for fifth generation (5G) millimeter-wave (mmW) communications. A novel band-switching input matching architecture based on the cross-connected transistors is proposed to achieve optimal dual-band input matching and $g_{m}$ -boosting. This architecture allows the dual-band input transistors to share …

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Analysis and Design of Power Amplifier Using Parallel-Combined Multisegment Transformer

Analysis and Design of Power Amplifier Using Parallel-Combined Multisegment Transformer 150 150

Abstract:

This letter presents a highly efficient power amplifier (PA) using a parallel-combined vertical multisegment transformer for 5G new radio (NR) applications operating in bands n257 and n258, in a 65-nm bulk CMOS process. A multisegment transformer facilitates a lower provided input impedance than a conventional transformer, enabling the PA to …

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A Compact, Wideband Complex Cascode Power Amplifier With LC Neutralization for VSWR-Resilient Operation in High-Density Phased Arrays

A Compact, Wideband Complex Cascode Power Amplifier With LC Neutralization for VSWR-Resilient Operation in High-Density Phased Arrays 150 150

Abstract:

This article proposes a design methodology for achieving intrinsic performance resilience in power amplifiers (PAs) against antenna impedance variations inherent to modern phased-array systems through the improvement of the PA output matching ( $S!_{22}$ ). This goal, however, presents a challenge for conventional cascode PAs due to their inherently high output impedance …

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A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance

A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance 150 150

Abstract:

This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a …

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A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation 150 150

Abstract:

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) …

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A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS

A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS 150 150

Abstract:

A dc-coupled analog single-ended (SE) transceiver (TRX) front-end supporting 224 Gb/s/lane is presented. It features SE-to-differential (S2D) and differential-to-SE (D2S) conversion, power-efficient broadband analog equalization, and noise suppression. Both the transmitter and receiver front-ends adopt pseudodifferential structures with dual-loop regulators to achieve a high power supply rejection …

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A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks

A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks 150 150

Abstract:

This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard $\pi $ -type equivalent circuits often suffer from bandwidth degradation due to …

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A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification 150 150

Abstract:

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that …

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