impedance

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A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy

A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy 150 150
Author(s): Seonghyun Park, Song-I Cheon, Haidam Choi, Sein Oh, Sohmyung Ha, Minkyu Je

Abstract:

This article presents an electrical bio-impedance (bioZ) spectroscopy integrated circuit (IC) that achieves both high-throughput and high-accuracy. The proposed phase-locked sampling (PLS) scheme, which employs a sampling phase-locked loop (SPLL) and a reference resistor ( $R_{\textit {REF}}$ ), enables fast and precise impedance demodulation. By extracting the impedance components through sampling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704052
Publisher: IEEE

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A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 150 150
Author(s): Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin D. Patino-Sosa, Philip Anschutz, Amanda Jacob, Keshav Ramachandra, Samuel Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe

Abstract:

This article presents a 32-channel time-multiplexed highly digital neural recording front-end (RFE) that exhibits sub- $8.8~\mu $ s recovery latency from large stimulation artifacts while delivering high-resolution data at the Nyquist rate. The RFE is time-shared across 32 channels for low-frequency electrocorticography (ECoG) recording and across four channels for high-frequency action potentials (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1053 – 1067
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3643367
Publisher: IEEE

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A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS

A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS 150 150
Author(s): Sungwon Kwon, Byung-Wook Min

Abstract:

This article presents a W-band active bidirectional vector-sum phase shifter (Bi-VSPS) using a bidirectional phase-inverting variable-gain amplifier (Bi-PIVGA) with back-gate biasing in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS. The Bi-PIVGA employs a neutralization technique that cancels the gate-to-drain capacitances of both active and inactive transistors in each signal direction. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699765
Publisher: IEEE

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A Third-Harmonic-Enhanced Triple-Push DCO Utilizing Source-Combining Technique

A Third-Harmonic-Enhanced Triple-Push DCO Utilizing Source-Combining Technique 150 150
Author(s): Qiyao Jiang, Zhuo Xu, Quan Pan, Pui-In Mak, Rui P. Martins, Jun Yin

Abstract:

This article presents a detailed investigation into optimizing the amplitude and phase of the transistor’s terminal voltages to generate a high 3rd-harmonic current in the millimeter-wave (mm-Wave) frequency. Based on the analysis, the digitally controlled source-combining triple-push (SCTP) oscillator is derived to significantly enhance the 3rd-harmonic current by introducing …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692500
Publisher: IEEE

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A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS

A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS 150 150
Author(s): Wei-Yu Lin, Nikhil Jain, Jun-Chau Chien

Abstract:

Implementing oscillators with harmonic engineering beyond 60-GHz poses significant challenges due to the need for small inductors resonating beyond 120 GHz. To address this issue, this work presents a 60-GHz standing-wave oscillator (SWO) with both second- and third-harmonic boosting for phase noise reduction. A triple-line resonator is proposed to sustain both …

Published in: IEEE Solid-State Circuits Letters
Page(s): 158 – 161
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3693153
Publisher: IEEE

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Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation

Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation 150 150
Author(s): Hao Yu, Zhaojing Fu, Lianbo Liu, Qiang Zhou, Taiyun Chi, Sensen Li

Abstract:

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667125
Publisher: IEEE

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A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE

A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE 150 150
Author(s): Yudai Yamazaki, Yohei Morishita, Sunghwan Park, Takaya Uchino, Chenxin Liu, Jun Sakamaki, Akihiro Egami, Ryosuke Hasaba, Ken Takahashi, Tomoki Abe, Tomohiro Murata, Yoichi Nakagawa, Takashi Tomura, Hiroshi Taneda, Kei Murayama, Makoto Tsukahara, Hiroko Ota, Yoko Nakabayashi, Ryuji Kinugawa, Takumi Kojima, Anyi Tian, Kotaro Ito, Chun Wang, Hans Herdian, Yi Zhang, Zheng Li, Wenqian Wang, Hongye Huang, Dingxin Xu, Sena Kato, Michihiro Ide, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Koji Takinami, Kenichi Okada

Abstract:

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1275 – 1293
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665184
Publisher: IEEE

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A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS

A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS 150 150
Author(s): Nayu Li, Ziyao Xiong, Botao Yang, Hang Lu, Yiwei Liu, Xiaokang Qi, Gaopeng Chen, Na Yan, Chunyi Song, Zhiwei Xu

Abstract:

This article presents a K/Ka-band transmit/receive (T/R) front-end for jointed sensing and communication (JSAC) applications. A reconfigurable matching network for both signal reception and transmission is realized using the proposed triple-coupled transformer (TCT) technique, achieving low power loss and a compact footprint. The T/R switch at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667736
Publisher: IEEE

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A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination

A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination 150 150
Author(s): Bo Pang, Fei You, Taotao Pang, Rongxing Qin, Zehua Xiao, Yingjie Liu, Yingyu Liu, Xinyu Wang, Junfu Guo, Songbai He

Abstract:

This article presents a 2–18 GHz high-efficiency CMOS nonuniform distributed power amplifier (NDPA) with a novel reconfigurable inductive termination technique for ultra-broadband efficiency enhancement. First, the inherent drawback of the degrading efficiency with growing frequency in a conventional non-reconfigurable NDPA architecture with multi-octave bandwidth is studied. A simple and effective reconfigurable …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665920
Publisher: IEEE

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